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How interaction happens between bins with different coverpoints without help of cross coverage

Posted by Subbi Reddy on Mar 23, 2021
Coverage #systemverilog #uvm #coverage How interaction happens between bins with different coverpoints without help of cross coverage Ex coverpoint covpt1 bins avar1; bins avar2; coverpoint covpt2 bins bvar1; bins bvar2; without using cross coverage needs ...

Question
Coverage

#systemverilog #uvm #coverage
Binding interface to dut in top

Posted by Pooja Pathak on Mar 14, 2021
UVM #uvm #uvm #bind #set #environment #test Hi, Please find my code on the edaplayground here: https://www.edaplayground.com/x/EDVr In the top module, I am instantiating the dut and then am trying to bind an interface to the signals on it. module tb_top; ...

Question
UVM

#uvm #uvm #bind #set #environment #test
function new() in user defined UVM classes

Posted by bachan21 on Mar 6, 2021
UVM new Function new() #uvm // constructor function new (string name, uvm_component parent); super. new (name, parent); endfunction: new Why do we have to declare new constructor in every extended UVM class as its already available in UVM base classes ...

Question
UVM

new Function new() #uvm
please provide links to learn GLS (gate level simulation)

Posted by Subbi Reddy on Mar 5, 2021
SystemVerilog GLS #systemverilog #uvm How to learn GLS (gate level simulation) please provide any web link or videos links...etc? ...

Question
SystemVerilog

GLS #systemverilog #uvm
How to find writing and reading wrong into or from the memory

Posted by Subbi Reddy on Mar 3, 2021
SystemVerilog #systemverilog #uvm How to find only few address are going into the wrong address in the large memory(1GB memory) Ex: 1. memory controller got it data, write on 19th address into the memory, but memory wrote in 21th address 2. memory control ...

Question
SystemVerilog

#systemverilog #uvm
How RAL knows automatically when ever DUT status registers changes

Posted by Subbi Reddy on Mar 2, 2021
UVM #uvm How RAL knows automatically when ever DUT status registers changes Ex: status register is changed from 0 to 1, immediately How RAL knowns the status register is changed from 0 to 1 vice versa ...

Question
UVM

#uvm
SystemVerilog: unexpected behavior while dealing with fork/join_none

Posted by rubendah on Feb 21, 2021
SystemVerilog #systemverilog #uvm mailbox #fork_joinnone Hi everyone, In the following code, my_mbx is an unbounded mailbox that can be populated from multiple sources at the same simulation time: virtual task mbx_monitor (); mbx_data_object mbx_data; ...

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SystemVerilog

#systemverilog #uvm mailbox #fork_joinnone
Setting using uvm_config_db

Posted by bachan21 on Feb 11, 2021
UVM #uvm #uvm_config_db I am trying to set values in my test class to different env instances using uvm_config_db. But the output is coming as 0 for both instances. The code is quoted below. What changes do I have to make to get expected output? Obsreved ...

Question
UVM

#uvm #uvm_config_db
Constraint solver failure on a rand variable with rand_mode(0)

Posted by rubendah on Feb 2, 2021
SystemVerilog #systemverilog #uvm #systemverilog #constraint Hi everyone, I've encountered the following failure: Solver failed when solving following set of constraints bit[31:0] id = 32'h0; rand packet_direction_vt my_variable= TRANSMIT; // ra ...

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SystemVerilog

#systemverilog #uvm #systemverilog #constraint
UVM Instance override for UVM objects

Posted by rag123 on Jan 25, 2021
UVM #uvm what is the right way to override a uvm_object with instance override? I have an extended transaction which will override the original transaction. ext_trans = extended_transaction:: type_id:: create ("ext_trans",, "hola"); In ...

Question
UVM

#uvm

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