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uvm monitor Access interface created by generate statement- Illegal operand for constant expression

Posted by Michaelotus on Apr 24, 2023
UVM I am running into a "Illegal operand for constant expression" when access an array of interface that was created by generate statement in testbench Here is my code- On the verilog side, I have interface sub_interface; endinterface interfac ...

Question
UVM
Why don't driver wait clock when driving empty sequences?

Posted by HanP on Apr 24, 2023
UVM In my sequence class wait_1_clock_c extends uvm_sequence; `uvm_object... function new... task body (); `uvm_info (get_full_name (), "wait 1 clock... ", UVM_LOW) endtask endclass //------------------------------------------------ class ...

Question
UVM
Parameterized Component registered via `uvm_component_utils Macro

Posted by TC_2017 on Apr 24, 2023
UVM Parameterized Component registered via `uvm_component_utils Macro Out of curiosity I was trying an example of running a parameterized test (registered via `uvm_component_utils macro). `include "uvm_macros.svh" `include "uvm_pkg.sv" ...

Question
UVM

Parameterized Component registered via `uvm_component_utils Macro
uvm_sequence randomization

Posted by Boogeyman on Apr 23, 2023
UVM #randomization #uvm_sequence Hi, I have query in uvm_sequence randomization. All the sequences are started by using seq.start(sequence_name) method.And, this will automatically randomize whatever present inside the sequence. But, if we explicitly rand ...

Question
UVM

#randomization #uvm_sequence
How to find debug

Posted by Lakshman07 on Apr 22, 2023
UVM How will you debug memory swap issue I.e. I am writing some data to addr 0x20 but due to some bug it is being written at location 0x40. Similarly, when I try to read from 0x40, I am getting the data written at addr 0x20. ...

Question
UVM
About the depth variable in uvm_object::copy source code

Posted by flhcherish on Apr 21, 2023
UVM #uvm_object copy depth Hi In uvm_object::copy method which inside UVM source code, there is one static variable named as depth. Could you help clarify why it is needed here, I have no idea what its purpose. Thank you Longhui ...

Question
UVM

#uvm_object copy depth
covergroup "per object" as opposed to "per instance"

Posted by Alex K. on Apr 21, 2023
UVM #coverage There are multiple instances of the same class containing a covergroup: class A; covergroup X {...} endclass class B; A a_inst [5]; for (int i = 0; i < 5; i ++) A.sample (); endclass I expected the above to generate coverage per instance, ...

Question
UVM

#coverage
Forever loop break

Posted by RB87 on Apr 21, 2023
UVM Forever Loop Break in UVM How the forever loop breaks in the following code snippet? My assumption is the execution should remain inside forever loop indefinitely as there is no break condition. But the execution exits the loop to my surprise. task ev ...

Question
UVM

Forever Loop Break in UVM
Getting issue in decoding the one bit STD_LOGIC generic datatype

Posted by Mayank98 on Apr 21, 2023
UVM Hi, I am trying to make verification plan using UVM. While instantiating my RTL code written in VHDL that has generic of one bit STD_LOGIC. I want to change the generic using `define or parameters in my UVM testbench. While changing the values of gene ...

Question
UVM
UVM_FATAL: default timeout of 9200 hit, indicating a probable testbench issue

Posted by jpms.suresh on Apr 20, 2023
UVM #delay uvm_components I am new to UVM and working on alu test bench. at every time i simulating it is giving the following error, after execution of Monitor Run Phase, please can any one suggest that where i have done wrong. Thanks in Advance. suresh. ...

Question
UVM

#delay uvm_components

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