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Sequence overriding from test.

Posted by sarth21 on Apr 5, 2021
UVM #uvm Application of Factory Overrides Hello, I am trying to override following sequences from build_phase of test. virtual function void build_phase (uvm_phase phase); env_configuration:: type_id:: set_type_override (config_one:: get_type ()); //con ...

Question
UVM

#uvm Application of Factory Overrides
Need of parameterization in UVM

Posted by bachan21 on Apr 5, 2021
UVM #ParameterizedClass #uvm I have observed that the extended UVM classes are often parameterized. For example, user defined driver class. What is the advantage of parameterizing user defined classes? How does it affect the UVM code? ...

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UVM

#ParameterizedClass #uvm
Can I get more basic UVM examples to improve my knowledge?

Posted by brain_storm on Apr 3, 2021
UVM #uvm #systemverilog #UVM I have been working as a Design Verification Engineer for a year now and am learning UVM hands-on. But, I would have learned more had I practiced UVM by myself by just having a basic DUT and writing UVM objects+components to v ...

Question
UVM

#uvm #systemverilog #UVM
UVM pipelined driver cookbook

Posted by rag123 on Mar 30, 2021
UVM #uvm I am going through the UVM code on the pipelined driver from cookbook and i dont understand how command phase and data phase execute in parallel? m_bfm.begin_transfer is a blocking call and doesnt not return until the command phase and data phase ...

Question
UVM

#uvm
Why are we driving the read data after two clocks in driver and monitor of a simple memory design?

Posted by brain_storm on Mar 29, 2021
UVM #uvm UVM Driver UVM monitor Design spec: https://verificationguide.com/systemverilog-examples/systemverilog-testbench-example-memory_m/ EDA Code: https://www.edaplayground.com/x/ezS The design spec says, "Read Operation: address and rd_en should ...

Question
UVM

#uvm UVM Driver UVM monitor
Randomization with uvm_do_with

Posted by kritikagoell on Mar 29, 2021
UVM #uvm `uvm_do_with #randomization Hi, I was trying to randomize the the order of read and write through uvm_do_with. In the following code 1.class ahb_wr_rd_seqs extends ahb_base_seq; 2. `uvm_object_utils(ahb_wr_rd_seqs) 3. function new(string name=&qu ...

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UVM

#uvm `uvm_do_with #randomization
Delay in signals at clocking block hierarchy w.r.t RTL hierarchy in waveform

Posted by GC on Mar 28, 2021
SystemVerilog #uvm #clockingblock Clocking Block #systemverilog input output skew There is a testbench env and I am working on some tests, I noticed that in the waveform if I pull a specific signal which is input to rtl from rtl hierarchy and pull the sam ...

Question
SystemVerilog

#uvm #clockingblock Clocking Block #systemverilog input output skew
uvm_backdoor and uvm_frontdoor parallel access to a register

Posted by debdip microsemi on Mar 27, 2021
UVM #uvm #UVM #RAL Hello, I am having one scenario where reg write is happening thru frontdoor access in one uvm_component run_phase. We know It takes couple of clock cycles to complete. For example I am initiating write at 50ns sim time and it is complet ...

Question
UVM

#uvm #UVM #RAL
Fully python flow over UVM: any feedback

Posted by haykp on Mar 25, 2021
UVM #uvm #python Dear Forum, I want to know your opinion about using python to fully replace UVM. There is kind of ready flow based on pyuvm,cocotb and pyconstraints. Which fully replace the UVM. No need to write UVM code, all these python packages will d ...

Question
UVM

#uvm #python
pipelined access of sequence from cookbook

Posted by rag123 on Mar 24, 2021
UVM #uvm I am looking at the UVM cookbook and i see the example with pipelined_item_done has 2 sequences one with unpipelined and another with pipelined. I see both the sequences have command and data phase separately. How is the first one non-pipelined a ...

Question
UVM

#uvm

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