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Broadcasting reset assertion event via uvm_event_pool

Posted by svl2 on May 4, 2023
UVM uvm_event_pool reset broadcasting Is it a good idea to use uvm_event_pool to broadcast reset assertion/de-assertion information across the UVM testbench components (rather than passing through vif)? Would like to trigger a stimuli from sequence, after ...

Question
UVM

uvm_event_pool reset broadcasting
does it make sense to have array of analysis implementations?

Posted by victorh on May 3, 2023
UVM UVM array analysis imp I have a design that has a repeated smaller block and the repetition is parameterized. In the UVM environment, it is easy to control the number of (agents, monitors,...) in build and connect phases, but when it comes to the scor ...

Question
UVM

UVM array analysis imp
OVM to UVM testbench conversion

Posted by sheetal saini on May 3, 2023
UVM Hello, We are converting our full chip testbench from OVM to UVM. Are there any big advantages to do so, as it will be a quarter of year effort. Will UVM testbench reduce time to run a single test also?(So, that regression time can be reduced) Regards ...

Question
UVM
sprint () method in UVM

Posted by yasirdv on May 2, 2023
UVM What is the purpose of value (@1364) in uvm_sequence_item (trans_collected)displayed by sprint () method? UVM_INFO./tb/wb/wb_monitor.sv(92) @ 78: uvm_test_top.env.wb.agents[0].mon [wb_monitor] Transfered collected:------------------------------------- ...

Question
UVM
randc in an variable within an array of objects

Posted by AL_verif on May 1, 2023
UVM randc #systemverilog #Arrays I tried to generate an array with different values each items (random value, not the index) my array declared as a randc, but it doesn't work for me: class fs_array; randc int unsigned array1 [6]; constraint c {fore ...

Question
UVM

randc #systemverilog #Arrays
Cannot create a component as it is not registered with a factory

Posted by meenu2k11 on Apr 27, 2023
UVM Hi When I try running a test, i get an error "Cannot create a component of type TEST_DIR_PATH/test_name> because it is not registered with the factory ". The test is registered with the factory `uvm_components_utils("testclass name&q ...

Question
UVM
UVM REGISTER SKIP REG2BUS

Posted by KARTHIKESAN NATARAJAN on Apr 27, 2023
UVM Advanced UVM Register skipping the reg2bus call. I am trying to find a way to selectively skip the reg2bus in the adapter when uvm register write is called. Thanks, ...

Question
UVM

Advanced UVM Register skipping the reg2bus call.
Two write_ function in Scoreboard pushing item to the same queue at the same time

Posted by elilee267 on Apr 26, 2023
UVM #UVM#write_function#round robin Hi Community, There is a 2-input, 2 output router and I am trying to write a scoreboard for this router My idea is based on the destination port number in the packet, whenever an input packet comes, push it to the corre ...

Question
UVM

#UVM#write_function#round robin
Hi, Can anybody give me the shortcut of specifying in testcase2 to pick up TOP_SEQ_NEW instead of TOP_SEQ without following entire hierarchy?

Posted by Jarvis_2304 on Apr 26, 2023
UVM ======> Existing Test Hierarchy <====== TESTCASE1: TOP_ENV TB_ENV_CFG TOP_SEQ ENET_SEQ ======> Corner case new test Hierarchy <====== TESTCASE2 (No cha ...

Question
UVM
Generic Driver on UVM

Posted by uvm_share on Apr 26, 2023
UVM #UVM #DRIVER #INTERFACE Hello, Can we have generic driver to receive and transfer Data for 2 differents bridge? Thanks, ...

Question
UVM

#UVM #DRIVER #INTERFACE

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