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UVM Coverage

Posted by rag123 on Jul 4, 2021
UVM #uvm Hi, 1) What is the right syntax for defining bins in coverage for enum? The below syntax doesnt seem to compile. typedef enum {READ, WRITE} kind_e; READ_WRITE: coverpoint trans.apb_cmd {bins apb_cmd [] = {[trans.apb_cmd. first: trans.apb_cmd. l ...

Question
UVM

#uvm
SVA assertion for realtime variables.

Posted by sarth21 on Jul 1, 2021
SystemVerilog #systemverilog #ASSERTION #uvm systemverilog #checkers Hi all, I am trying to run following code to check a fixed delay value 4440ps. I want difference of two realtimes' to be exactly equal to 4440ps. The difference is all correct when ...

Question
SystemVerilog

#systemverilog #ASSERTION #uvm systemverilog #checkers
Guidelines for using analysis port in monitor

Posted by bhupeshpaliwal on Jun 29, 2021
SystemVerilog #systemverilog #uvm UVM monitor analysis port In reference to analysis port used in system verilog or UVM monitor, is there any specific guidelines on number of analysis port to be used? While I understand from SV LRM perspective there is no ...

Question
SystemVerilog

#systemverilog #uvm UVM monitor analysis port
Which UVM API can provide list of uvm_objects at any given instance?

Posted by superUVM on Jun 18, 2021
UVM #uvm I need to find list all UVM objects active at a given instance for debug. Which API shall provide me this info? ...

Question
UVM

#uvm
Difference between uvm_transaction and uvm_sequence_item

Posted by Blitzz0418 on Jun 13, 2021
UVM #uvm hi Can someone tell me the difference between uvm_transaction and uvm_sequence_item? and how are they different in terms of use in UVM environment. thanks ...

Question
UVM

#uvm
Executing function at last after all functions

Posted by verific_engi on Jun 9, 2021
UVM #uvm I tried to create a scoreboard and declared the analysis ports using `define and started write functions out of phases in the scoreboard. Now I want to define a checker function to compare and want this function to execute at last after all write ...

Question
UVM

#uvm
Write method in scoreboard throws an error

Posted by verific_engi on Jun 3, 2021
UVM #uvm #UVM #scoreboard I have created a scoreboard and instead of implementing function void write() I have renamed it as write_mon(). UVM throws an error xmelab: *E,CUVUNF Hierarchical name component lookup failed for 'write' at 'uvm_pk ...

Question
UVM

#uvm #UVM #scoreboard
Ending a Test in Uvm

Posted by sasi_8985 on Apr 23, 2021
UVM #uvm #uvm # sequence UVM Driver Hi all, I had a doubt in an example given in verification guide website. EXAMPLE CODE In the above example there is a forever loop in mem_driver run phase task. if its forever then how does it end doesn't it get st ...

Question
UVM

#uvm #uvm # sequence UVM Driver
To Check clock alignment using system verilog assertion

Posted by praveen1705 on Apr 12, 2021
SystemVerilog #SVA #systemverilog #ASSERTION #uvm Hi, I have in_clk and in_clk_b(both are compliment to each other)clocks and clk_out_enable signal and the output signal is clk_out (another clock) How can i write a system verilog assertion to check clk_ou ...

Question
SystemVerilog

#SVA #systemverilog #ASSERTION #uvm
Casting in UVM

Posted by maazlee on Apr 6, 2021
UVM $cast casting #uvm Hi, I am trying to cast an object in a build phase as shown below. $cast(m_cpu_config[0], name); // where as the "name" is a type string and it holds the design hierarchy "top.a1.b2.c3.dv.rim.get_config_object()" ...

Question
UVM

$cast casting #uvm

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