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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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Ask a Question
UVM RAL
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  1. Runtime addition/deletion of Register in RAL Model

    Posted by shreypatel7 on Feb 25, 2015
    UVM RAL RAL register UVM Hi, I am implementing RAL model. I am dealing with a specification, where I need to dynamically create or delete registers depending on some logic. The number of registers that will be added, can be a large number; So I can't ...

    Question
    UVM
    RAL RAL register UVM

  2. Register Backdoor Issue

    Posted by shreemant.vats on Jan 30, 2015
    UVM uvm RAL UVM RAL Backdoor Write hdl_path Cookbook: Registers/BackdoorAccess Hi all, I am getting an error while accessing my dut register via backdoor as:- UVM_ERROR: set: unable to locate hdl path (dut.reg1) # Either the name is incorrect, or you may ...

    Question
    UVM
    uvm RAL UVM RAL Backdoor Write hdl_path Cookbook: Registers/BackdoorAccess

  3. Issue in setting up Hdl path in RAL

    Posted by kothaluri rajashekhar on Jan 8, 2015
    UVM RAL unable to locate hdl path Hi, Need help. I am facing an issue in setting up hdl path. Using back door access, this is the access hdl path: top.dut_i.x_i.y_i.z_i.reg Here top- Top Module dut_i- dut Module instance name x_i- x Module instantiated in ...

    Question
    UVM
    RAL unable to locate hdl path

  4. Shared address maps in uvm_reg_block

    Posted by ash7 on Dec 23, 2014
    UVM uvm RAL uvm_reg_map uvm_reg_block I have a top level uvm_reg_block with 2 maps, A and B. I add a subblock of type uvm_reg_block named C to both using add_submap(see below) this.A= create_map("A", `UVM_REG_ADDR_WIDTH'h0, 4, UVM_LITTLE_EN ...

    Question
    UVM
    uvm RAL uvm_reg_map uvm_reg_block

  5. Mirror(Difference In Values)

    Posted by shreemant.vats on Dec 11, 2014
    UVM uvm Register abstraction Layer RAL uvm register sequences Hi All, In one of my register sequences the very first method I am using is get_mirrored_value. There after I am calling get_reset method which I know will return the reset values configured in ...

    Question
    UVM
    uvm Register abstraction Layer RAL uvm register sequences

  6. Register Layer Modelling (R.A.L.) Read Data

    Posted by hvgbl on Aug 8, 2014
    UVM RAL Read Method hello Everyone.. I build a register Model, But having some warnings and errors. Warning: uvm_reg.svh (1632) @ 31: reporter [RegModel] Register 'block_obj.reg2' is not contained within map 'uvm_test_top.env_obj.agt_obj.se ...

    Question
    UVM
    RAL Read Method

  7. UVM RAL Broadcast write support

    Posted by nsshah on May 13, 2014
    UVM uvm register RAL broadcast writes aliased registers Does the register layer support broadcast writes (ie a single write actually writes multiple registers)? ...

    Question
    UVM
    uvm register RAL broadcast writes aliased registers

  8. Can uvm register model which support backdoor operation included in a package?

    Posted by seabeam on May 1, 2014
    UVM uvm_reg frontdoor backdoor hierarchy reference RAL Package Hi all: The uvm register model backdoor use direct hierarchy reference register of DUT. Now register model is constructed in env: class ahb_env extends uvm_env; ahb_reg_model reg_model;... fun ...

    Question
    UVM
    uvm_reg frontdoor backdoor hierarchy reference RAL Package

  9. Special register(s) with fields based on a mode

    Posted by NickZ on Apr 16, 2014
    UVM RAL uvm register registers uvm_reg_block Hi, I've been tasked with modeling a register block for a semi-legacy module that includes a register scheme that I have not come across in RAL literature. The basic idea is that there exists a register ca ...

    Question
    UVM
    RAL uvm register registers uvm_reg_block

  10. RAL UVM_ERROR: get: unable to locate hdl path mem_dut.mem[5] # Either the name is incorrect, or you may not have PLI/ACC visibility to that name

    Posted by Chandra Bhushan Singh on Mar 21, 2014
    UVM RAL Hi, I am compiling the mem_dut with the nvopt option in questa sim still its not able to find the hdl path, what may be the posible causes?. And i am sure name is correct. ...

    Question
    UVM
    RAL

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