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Getting error in sequence

Posted by Manirama on Aug 20, 2020
UVM #uvm The is working in synopsis VCS. while I am running the same code in Aldec am getting the below error. Error: VCP5235 D:/verification Components/write_seq.sv: (28, 63): Class sequence has no parameters. ...

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UVM

#uvm
How to write a UVM Sequence

Posted by rr2007 on Aug 11, 2020
UVM #uvm #systemverilog #sequence uvm sequence item Hi, I have a doubt in uvm_sequence creation. In the body of a uvm_sequence do I need to write 6 steps for generating a sequence or create req start_item(req) req.randomize() finish_item(req) is these ste ...

Question
UVM

#uvm #systemverilog #sequence uvm sequence item
uvm_config_db get usage

Posted by Pavan Acharya G on Aug 10, 2020
UVM #uvm uvm uvm_config_db Hi, Can the cfg be set in the lower hierarchy and get at hierarchy? For ex: //check_env.sv (build phase) uvm_config_db#(cfg_check)::set(uvm_root::get(), "*", "cfg_h", cfg_h); //check_test.sv (build phase) uvm ...

Question
UVM

#uvm uvm uvm_config_db
Disable uvm_info from individual component

Posted by Jack Bryan on Aug 6, 2020
UVM #uvm Dave Rich chris sue We have more than 500 components(agents,drivers,monitors etc) in our test bench. We get a lot of displays from each of them usnig uvm_info Is it possible to disable/enable display from a particular component. PS- All component ...

Question
UVM

#uvm Dave Rich chris sue
Prioritize write function call from UVM monitor

Posted by suhas.ns on Aug 6, 2020
UVM #systemverilog #uvm #monitor #UVM #scoreboard I'm using UVM based VIP for the AXI traffic generation. We have a scenario where, the write and read is sent at the same time to the design. The monitor captures the address ended transactions and it ...

Question
UVM

#systemverilog #uvm #monitor #UVM #scoreboard
Scope resolution operator::

Posted by tejasakulu on Aug 5, 2020
UVM #uvm #systemverilog Randomization Scope Resolution Hi class mxsclk_ver0_sequence # (type T = sys:: mxsclk_ver0_params) extends uvm_sequence # (mxsclk_ver0_seq_item_base); typedef T:: clock_type_t clk_cntrl_type_t; mxsres_ver0_pin_mode_seq # (sys:: mxs ...

Question
UVM

#uvm #systemverilog Randomization Scope Resolution
UVM_NO_DPI Option usage

Posted by rr2007 on Jul 31, 2020
UVM #systemverilog #UVM #uvm uvm dpi Systemverilog DPI Hi, Is the UVM DPI same as Systemverilog DPI inorder to make C and other programming languages compatible with systemverilog? I am seeing the UVM_NO_DPI option in UVM related testbencheS. What is the ...

Question
UVM

#systemverilog #UVM #uvm uvm dpi Systemverilog DPI
Running two asynchronous sequences

Posted by digitalo on Jul 24, 2020
UVM #sequencer #uvm I'm fairly new to UVM and running a UVM verification based on Easier UVM. I defined two agents with their respective drivers and sequences. Each agent alone performs its job as expected, but as soon as I enable both of them, the f ...

Question
UVM

#sequencer #uvm
Backdoor RAL read issue

Posted by alexkidd84 on Jul 15, 2020
UVM backdoor backdoor read_wrie #uvm bit size Hi, I'm trying to read (RAL) via BACKDOOR this RW register (40 bits width), after performing a FRONTDOOR write (the FRONTDOOR read works properly): uvm_reg urm_reg [$]; uvm_reg_field urm_reg_field [$]; ...

Question
UVM

backdoor backdoor read_wrie #uvm bit size
Driving an internal net in UVM

Posted by tejasakulu on Jul 11, 2020
UVM #uvm #systemverilog Hello Everyone, I have an internal net called wire P_HOOK under a design. My requirement is to drive this signal in UVM sequence How do i do that so far i did interface test1 (input clk); logic p_hook; endinterface bind desig ...

Question
UVM

#uvm #systemverilog

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