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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
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    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
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    • Techniques & Tools

      • Verification IP
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      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
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      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Formal 101: Optimizing Constraints - 5/11
      • Three CDC Glitches - 5/18
      • User2User - 5/26
      • Webinar Calendar

    • On-Demand Webinars

      • Fault Campaign for Mixed-Signal
      • Low Power Verification
      • CDC+RDC Analysis
      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • All On-Demand Webinars

    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings

    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
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      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive

    • About Us

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      • Contact Us

    • Training

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Ask a Question
UVM
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Results

  1. Re: Parameterized Component registered via `uvm_component_utils Macro

    Posted by dave_59 on Apr 28, 2021
    In reply to TC_2017: You are correct about the macro getting expanded or compile time whereas specialization occurs at elaboration. So only a single string "test#(BITWIDTH)" gets registered with the default value of the parameter. Any attempts t ...

    Reply
    UVM
    Parameterized Component registered via `uvm_component_utils Macro

  2. UVM sequence

    Posted by yunusmujawar on Apr 28, 2021
    UVM Hi, 1.Is it possible to access the inbuilt response queue and request queue which is there inside a sequencer if yes then is it possible to take a handle of that queue and access the response in another UVM component class. 2.i want to store the data ...

    Question
    UVM

  3. Re: UVM sequence

    Posted by chr_sue on Apr 28, 2021
    In reply to yunusmujawar: It is a little bit unclear to me what your intention is. I guess you want to use transaction data from the slave in the master and also transaction data from the master in the slave. Is this correct? ...

    Reply
    UVM

  4. Re: Issue with UVM Driver to send request transactions on parallel bus

    Posted by Nagarjuna Chary on Apr 27, 2021
    In reply to cgales: Thanks much cgales! I was struggling to create the parallel threads which would get requests from the sequence class & drive the dut and was focusing on packing them in a single fork/forever construct. Thanks also for the usage of ...

    Reply
    UVM
    back2back parallel bus

  5. Issue with UVM Driver to send request transactions on parallel bus

    Posted by Nagarjuna Chary on Apr 27, 2021
    UVM back2back parallel bus Hi, I read the blog post on UVM Driver models and am trying to implement a driver for the case (simplified) below. On the interface, there is an address channel & a Data channel. On the address bus, four addresses are sent b ...

    Question
    UVM
    back2back parallel bus

  6. Problem running a reactive sequence in a forever loop

    Posted by szy0014 on Apr 27, 2021
    UVM reactive sequence #driver forever block fork join Hi All, I tried to write a reactive sequence that constantly monitors a pin on the output of the DUT and take some sequence of actions when it sees one. However, I cannot figure out how to push the seq ...

    Question
    UVM
    reactive sequence #driver forever block fork join

  7. Re: Problem running a reactive sequence in a forever loop

    Posted by megamind on Apr 27, 2021
    In reply to chr_sue: I understood what you are saying, and I believe that makes sense unless I think further and come up with some more questions on this if in case. Please let me think through if reactive slave with driver sensing the bus transactions is ...

    Reply
    UVM
    reactive sequence #driver forever block fork join

  8. Re: Issue with UVM Driver to send request transactions on parallel bus

    Posted by cgales on Apr 27, 2021
    In reply to Nagarjuna Chary: You have some issues in the parallel driver where you are trying to fork processes when you receive packets. The ideal implementation is to have the address/data processes running all the time and waiting for transactions to a ...

    Reply
    UVM
    back2back parallel bus

  9. Re: Issue with UVM Driver to send request transactions on parallel bus

    Posted by Nagarjuna Chary on Apr 27, 2021
    In reply to cgales: Here is the link. file name being discussed about is "dut_parallel_driver.sv" ...

    Reply
    UVM
    back2back parallel bus

  10. Re: Problem running a reactive sequence in a forever loop

    Posted by chr_sue on Apr 27, 2021
    In reply to megamind: I do not understand why you want to do simple things complicated. The driver/sequencer have a built-in response handling mechanism. The monitor does not. You have to implement this mechanism on your own. This is significant effort an ...

    Reply
    UVM
    reactive sequence #driver forever block fork join

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