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Ask a Question
UVM RAL
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  1. How to maintain multiple mirror value in a register

    Posted by Usr021 on May 29, 2016
    UVM uvm RAL mirror value Hi all, I am new to RAL and recently I run into a case in which one register requires multiple mirror values to be maintained. I am hoping anyone could help me on this topic. For demonstration, let's assume DUT has 2 register ...

    Question
    UVM
    uvm RAL mirror value

  2. Driving through RAL.

    Posted by kapil khare on May 29, 2016
    UVM RAL Hello sir, I am new in UVM. My question is based upon the RAL Adapter class. sir as per my knowledge, in uvm environment, uvm_driver is used to sending the request to sequence to generate the transactions and send to driver by different methods wh ...

    Question
    UVM
    RAL

  3. RAL

    Posted by gopal_susarla on May 17, 2016
    UVM RAL DUT instantiates module A module A instantiates module B & module C. Module B is a APB slave and module C is a APB master. How do I verify RAL in module B? I have an APB agent that I need to 'connect' to module B to control the APB i ...

    Question
    UVM
    RAL

  4. Accessing successive numbered registers in SV/UVM

    Posted by shridutt.nv on Jan 6, 2016
    UVM RAL Cookbook: Registers Hi, I am looking to access numbered registers: reg0, reg1, reg2,... and stat0,stat1,stat2,... but the number of registers that I access is dependent on a variable n For Eg: n=1 => reg_blk.reg0.write(status,value0); reg_blk.s ...

    Question
    UVM
    RAL Cookbook: Registers

  5. Executing RegModel translation sequence on sequencer, does not have an upstream sequencer defined. Execution of register items available only via direct calls to 'do_rw_access'

    Posted by Jayakirthi Reddy on Dec 9, 2015
    UVM RAL Cookbook: Registers/ModelStructure Hi, I am trying implement RAL. I am getting following UVM_WARNING and my test is hanging. UVM_WARNING /synopsys/vcs_mx_J-2014.12-sp3/etc/uvm/reg/uvm_reg_sequence.svh(137) @ 0: uvm_test_top.env.sagent.ssp_seqr@@s_ ...

    Question
    UVM
    RAL Cookbook: Registers/ModelStructure

  6. I need to know when a W1C register is written

    Posted by lucaskoelho on Oct 13, 2015
    UVM RAL WC uvm register w1c Hi there, I have a W1C register which has the funcionality to reset a counter. If I can't check the value into register, because it will be always zero, how I can know that there's a write operation in the register? H ...

    Question
    UVM
    RAL WC uvm register w1c

  7. Can one use values from a previously run sequence to constraint a future sequence?

    Posted by owenjarvie on Oct 7, 2015
    UVM RAL `uvm_do_on virtual sequence virtual sequencer Hi, My current situation is that I have an SPB UVC which implements RAL sequences. These sequences fine, having tested the SPB UVC extensively. The SPB sequences are used to drive DAI register values, ...

    Question
    UVM
    RAL `uvm_do_on virtual sequence virtual sequencer

  8. RAL Concept, Benefits?

    Posted by withankitgarg on Aug 24, 2015
    UVM uvm RAL uvm_reg uvm_reg frontdoor backdoor uvm_reg_adapter Hi, I have understood how RAL is used in UVM. But still I am not clear about the benefits of using RAL. Point 1.) Backdoor access can be done using the hierarchical path without RAL then how R ...

    Question
    UVM
    uvm RAL uvm_reg uvm_reg frontdoor backdoor uvm_reg_adapter

  9. Getting UVM_ERROR for Register Abstraction Layer, But UVM_ERROR's At the end of simulation shown as 0

    Posted by shreemant.vats on Aug 17, 2015
    UVM uvm RAL Getting UVM_ERROR as follows during simulation: # UVM_ERROR: get: unable to locate hdl path top.svr.sw_up.device.MAN_REGS.rdt_life_tim # Either the name is incorrect, or you may not have PLI/ACC visibility to that name # UVM_INFO /home/shreema ...

    Question
    UVM
    uvm RAL

  10. RAL_model

    Posted by Nijanthan on Mar 31, 2015
    UVM RAL Ral model how to write Front door access code? ...

    Question
    UVM
    RAL

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