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Incorrect use of virtual interface

Posted by Abuzar Gaffari on May 12, 2023
UVM I have two interfaces, axi_vif and reset_vif, I did set these interfaces in my top module and get inside base_test. In my testcase I want to do assign axi_vif.clk = reset_vif.aclk but I'm getting error as virtual interfaces variables are not perm ...

Question
UVM
Message Reporting

Posted by Sayyed on May 12, 2023
UVM uvm message reporting Hi, I am trying to filter out messages with a particular ID i.e "UVM_DBG" to a seprate log file i.e "debug_lib.log". I am expecting the messages in log file at the execution time, but messages are written to t ...

Question
UVM

uvm message reporting
Regarding timing constraint for input

Posted by Swathi BN on May 12, 2023
UVM Hi I want to drive inputs we(write enable), cpu_addr and cpu_data for oly one clock cycle i mean on the same clock and for 1 clock cycle i am not able to do that. Can anyone suggest me using wt we can drive 3 signals on same clock & for 1 clock cy ...

Question
UVM
uvm declare p_sequencer

Posted by ayasaad234 on May 11, 2023
UVM uvm declare p_sequencer where should i put this declaration in sequence or sequencer? uvm_declare_p_sequencer(SEQUENCER_NAME) ...

Question
UVM

uvm declare p_sequencer
Can I send parent sequence item and child sequence item at the same time to the Driver?

Posted by UVM_LOVE on May 11, 2023
UVM #sequence Hi. I have one parent sequence item class and inherited one child class. parent sequence item has only A property, child class has only B Property. If I send a parent sequence item and a child sequence item at the same time to the Driver in ...

Question
UVM

#sequence
How to write and read register in RAL

Posted by uvmbee on May 11, 2023
UVM Hello, My register model looks be generated normally. The build phase in env was regmodel = ral_block_cfg_regmodel:: type_id:: create ("regmodel", this); regmodel.build (); regmodel.default_map.set_base_addr ('h11da00f0); regmodel.add_h ...

Question
UVM
Integration of a DUT with two top_level modules in a UVM SV testbench

Posted by verif_25 on May 11, 2023
UVM #uvm #testbench #verification #System verilog #interface Hello all, I have a design with two top-level modules, these two tops are used based on the memory model i choose (whether it is a single or dual port memory) my question isas follows: in my top ...

Question
UVM

#uvm #testbench #verification #System verilog #interface
What's the best class naming convention for re-usability in higher level testbenches (avoid multiple classes with same names)

Posted by jnbkeller on May 10, 2023
UVM uvm naming convention class names reuse Example first: Assume a testbench for a DUT has an environment class called env. Assume I have multiple testbenches for multiple DUTs, each having an env class name. Now I create a 'multi-device' testb ...

Question
UVM

uvm naming convention class names reuse
Time elapsing and hardware mirroring in RAL

Posted by uvmbee on May 10, 2023
UVM Hello, I have a fundamental question about using RAL. In the reference, The general sequence task can be repleaced to RAL sequence as below. //General Sequence task virtual task body (); `uvm_do_with (req, {addr == ’h0; kind == UMV_READ;}); `uvm_do_wi ...

Question
UVM
How to print UVM Report Summary UVM1.2 with UVM_NONE verbosity

Posted by aditya.polepeddi on May 9, 2023
UVM #UVM #REPORT #SUMMARY In UVM1.2, UVM Report Summmary has verbosity of UVM_LOW. I am using UVM_NONE as the global verbosity. Due to this UVM report summary is not getting printed at the end of simulation. I have tried passing Quote: +uvm_set_verbosity= ...

Question
UVM

#UVM #REPORT #SUMMARY

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