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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
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    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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      • Coverage Forum

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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • Continuous Integration - March 28th
      • Questa Verification IQ - April 11th
      • SystemVerilog Assertions
      • SoC Design & Functional Safety Flow
      • 2022 Functional Verification Study
      • Design Solutions as a Sleep Aid
      • CDC and RDC Assist
      • Formal and the Next Normal
      • Protocol and Memory Interface Verification
      • Webinar Calendar

    • On-Demand Library

      • Practical Flows for Continuous Integration
      • Lint vs Formal AutoCheck
      • The Three Pillars of Intent-Focused Insight
      • Formal Verification Made Easy
      • Fix FPGA Failures Faster
      • HPC Protocols & Memories
      • FPGA Design Challenges
      • High Defect Coverage
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Complex Safety Architectures
      • Data Independence and Non-Determinism
      • Hierarchical CDC+RDC
      • All On-Demand Recordings

    • Recording Archive

      • Aerospace & Defense Tech Day
      • Exhaustive Scoreboarding
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • Visualizer Debug Environment
      • Preparing for PCIe 6.0: Parts I & II
      • Automotive Functional Safety Forum
      • Siemens EDA Functional Verification
      • Improving Your SystemVerilog & UVM Skills
      • All Webinar Topics

    • Conferences & WRG

      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences

    • Siemens EDA Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification IQ
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    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
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    • Training

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Ask a Question
#coverage
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Results

  1. Understanding triggering cover groups using.sample()

    Posted by aashishs2603 on May 23, 2021
    SystemVerilog #coverage #UVM #Coverage #covergroup coverpoint sample Hello I am looking at some code as below (only psedo code posted.) and curious how.sample() works for triggering cover group. covergroup A option.per_instance = 1; //some code here. bins ...

    Question
    SystemVerilog
    #coverage #UVM #Coverage #covergroup coverpoint sample

  2. System verilog coverage: map coverage from different array elements to same coverpoint

    Posted by Chakrakirthi on May 13, 2021
    Coverage #systemverilog #coverage Hi, In Systemverilog is there a way to get coverage from elements of Array to the same coverpoint. Say int arr [10]; // array of elements covergroup cov_arr; coverpoint arr {bins arr_b = {[1: 20]};} // I want coverage fro ...

    Question
    Coverage
    #systemverilog #coverage

  3. transition coverpoint sampling issue!!

    Posted by Malai_21 on May 11, 2021
    Coverage #coverage #covergroup coverage transition bins Hello all, I have an issue with transition coverpoint, it is not getting sampled, whenever the ".sample" method is called. But it is getting sampled when there is a sampling event with cove ...

    Question
    Coverage
    #coverage #covergroup coverage transition bins

  4. Coverage for enum

    Posted by rag123 on May 8, 2021
    UVM #coverage Hi, I am trying to write a coverage for enum which is dynamic array and i am not able to completely write it. Here is my code. Can anyone help me? typedef enum bit[1:0] {IDLE, BUSY, NONSEQ, SEQ} transfer_t; In transaction class rand transfer ...

    Question
    UVM
    #coverage

  5. Literature on: On-the-fly stimuli generation based on coverage collected

    Posted by 1978bubun on May 6, 2021
    Coverage #coverage Constrained radomization with Machine Learning artificial intelligence stimulus in system verilog Hello, Could anybody provide some links to literature (books/papers/videos/blogs) on how to adaptively create stimuli to maximize coverage ...

    Question
    Coverage
    #coverage Constrained radomization with Machine Learning artificial intelligence stimulus in system verilog

  6. Coverage collection of algorithmic IP conducted in the sequence

    Posted by Michael54 on May 2, 2021
    Coverage #coverage #coveragecollectionfromseq Hi, I am looking for ideas/papers, for the next case: Started working on legacy IP- Imaging and video processing IP. All the blocks in the IP have a reference model handled by an algorithms team, let's ca ...

    Question
    Coverage
    #coverage #coveragecollectionfromseq

  7. Way to implement cross coverage so that 1 hit in the cross is considered to be covered.

    Posted by Nimisha Varadkar on Mar 23, 2021
    Coverage #coverage Bins coverage bin cross coverage cross coverage bins Hi All, I'm trying to implement a cross coverage for variable-> size, index, ways and parameter n(size,ways, index, n). I want to implement it in a way that whenever a single ...

    Question
    Coverage
    #coverage Bins coverage bin cross coverage cross coverage bins

  8. How interaction happens between bins with different coverpoints without help of cross coverage

    Posted by Subbi Reddy on Mar 23, 2021
    Coverage #systemverilog #uvm #coverage How interaction happens between bins with different coverpoints without help of cross coverage Ex coverpoint covpt1 bins avar1; bins avar2; coverpoint covpt2 bins bvar1; bins bvar2; without using cross coverage needs ...

    Question
    Coverage
    #systemverilog #uvm #coverage

  9. How to get a non-duplicate randomized value from coverage?

    Posted by UVM_LOVE on Mar 17, 2021
    Coverage #coverage Dear All, Currently I'm learning the coverage. It's very powerful methods for verification I think. But I'v got a problem that I'm trying to get a non-duplicated randomized value. Here is the code. class packet;   ra ...

    Question
    Coverage
    #coverage

  10. Using Macros to create Covergroups

    Posted by __SarVesH on Mar 10, 2021
    SystemVerilog #systemverilog macros #coverage Hi all, I am trying to automate the process of creating covergroups and sampling of bins in it. Below is a code snippet. class abc; \ `define CVG (STR, MAX) \ covergroup ``STR``; \ STR``_arg2: coverpoint var_i ...

    Question
    SystemVerilog
    #systemverilog macros #coverage

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