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Is virtual seqr is required for virtual sequence?

Posted by abhi.khati7274 on Oct 22, 2021
UVM #uvm #UVM #virtual_sequences Hi, suppose i have a virtual sequence, is it compolsory to have a virtual seqr in our env? If virtual sequence is there then its obvious that we need virtual seqr? ...

Question
UVM

#uvm #UVM #virtual_sequences
Multiple packet in sequence and how to send those packet to specific seqr?

Posted by abhi.khati7274 on Oct 22, 2021
UVM #sequence #uvm hello i have been asked in 1 interview, if there are multiple packet in single sequence. if i want to send the specific packet to specific sequencer? how do we do that? ...

Question
UVM

#sequence #uvm
Default sequence in UVM

Posted by Malai_21 on Oct 13, 2021
UVM #uvm #sequence default_sequence Hello all, In UVM, default sequences can be used to start a sequence. I can see many replies in this forum regarding default sequences say "It is not recommended to use default sequences in test". Could you pl ...

Question
UVM

#uvm #sequence default_sequence
Why set_type_override() is always called after super.build()

Posted by aaaaaa on Oct 8, 2021
UVM #uvm #uvm #factory Is it because uvm component structure need to be built first? ...

Question
UVM

#uvm #uvm #factory
In AXI VALID/READY Handshake we have 3 scenarios how to write Assertion

Posted by SUNODH on Oct 5, 2021
SystemVerilog #systemverilog #ASSERTION #uvm #assertion #AXI AMBA AXI 3 In AXI we know we have VALID/READY handshake to transfer data and control information. Transfer occurs only when both the VALID and READY signals are HIGH, but here we have 3 scenario ...

Question
SystemVerilog

#systemverilog #ASSERTION #uvm #assertion #AXI AMBA AXI 3
uvm scoreboard OOO

Posted by svq on Sep 30, 2021
UVM #uvm #UVM #scoreboard Hi, I came across a interview question to write a scoreboard for for a design which has input id is out of order while output is in order? How do we approach this problem? Should we know the expected first id in this case and jus ...

Question
UVM

#uvm #UVM #scoreboard
Is there any reason for sequence is relative with build_phase and sequencer is relative connect_phase?

Posted by UVM_LOVE on Sep 28, 2021
UVM #uvm I have been trying to understand sequence from test in UVM, I would came across test class as the below, This example looks like "start" used for running sequencer. but as you can see, In build_phase, only implemented with sequence. No ...

Question
UVM

#uvm
base_test doesn't need to implement uvm_config_wrapper?

Posted by UVM_LOVE on Sep 27, 2021
UVM #uvm Dear All, I'm trying to understand the usage of UVM_TESTNAME and some test and sequences. I have made snippet code as the below, When I run " +UVM_TESTNAME=test2 ", then yapp_5_packet sequence has been run, that's what I expec ...

Question
UVM

#uvm
UVM Compare method does not give all mismatches

Posted by muhammadsalmanafzal on Sep 7, 2021
UVM #uvm #systemverilog #UVM Hey there, hope you are all doing well. I'm starting UVM and practicing on it. I'm having a rather odd problem that when I use compare method to check for mismatches, it always gives only single mismatch. Although, w ...

Question
UVM

#uvm #systemverilog #UVM
solver fails to solve easy constraints

Posted by nimrodw on Sep 2, 2021
UVM #constraint #randomization #uvm #systemverilog #queues Here are the constraints the solver is unable to solve int int_q [$] = {0, 1, 2}; rand int q_size; rand int rand_int_q [$]; constraint easy_constraint_c {q_size inside {[3: 666]}; rand_int_q. si ...

Question
UVM

#constraint #randomization #uvm #systemverilog #queues

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