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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
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      • Power Aware CDC Verification
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    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
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      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

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      • Formal-Based Technology: Automatic Formal Solutions
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      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
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      • Specification to Testplan
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      • Bus Protocol Coverage
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • U2U MARLUG - January 26th
      • Creating an Optimal Safety Architecture  - February 9th
      • The ABC of Formal Verification - February 11th
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Results

  1. Re: Delay between driver driving the interface signals and monitor sampling the same

    Posted by Rahulkumar on Jan 16, 2020
    In reply to tpan: When you sample the data at posedge of clock then you get the value it had. you won't get the new value which you are driving at that clock edge. //SystemVerilog Scheduling: Evaluate the Right-Hand-Side (RHS) of all nonblocking assi ...

    Reply
    UVM

  2. Re: Sequence ends quickly

    Posted by Rahulkumar on Jan 16, 2020
    In reply to tpan: This may be due to objection isn't raised. when you don't raise the objection, run phase will finish in 0 simulation time. So raise the objection in your test case run/main phase. //uvm test case main phase   virtual task main_ ...

    Reply
    UVM

  3. Re: Setting a sequence item Param from another sequence

    Posted by Rahulkumar on Jan 14, 2020
    In reply to UVM_learner6: class seq1 extends.. rand int a, b; endclass   class seq2 extends.. rand int data; rand int a, b; constraint c1 {data == a * b;} endclass   ///test case seq1. randomize (); seq1. start ();   seq2. randomize () with {a == seq1.a; ...

    Reply
    UVM

  4. Re: Setting a sequence item Param from another sequence

    Posted by Rahulkumar on Jan 13, 2020
    In reply to UVM_learner6: Quote: Hi, I have a write control sequence item and some rand Params, example a and b, declared inside. It has a corresponding write sequence. I also have a write data sequence item and some other rand params declared, example da ...

    Reply
    UVM

  5. Re: What is a valid Argument to run_test()

    Posted by Rahulkumar on Jan 11, 2020
    In reply to Have_A_Doubt: It won't generate error. did you check the code of uvm_agent and uvm_test? Both of these class are extended from the uvm_component. These classes are just wrapper over the uvm_component class. They don't contain any spe ...

    Reply
    UVM
    valid Argument to run_test()

  6. Re: Cross model reference

    Posted by Rahulkumar on Jan 10, 2020
    In reply to venkatasubbarao sutrave: you are using the cfg handle inside the test class which isn't created in the class. I fix some of the issues but still long way to go. you are using some of the deprecated items also. https://www.edaplayground.co ...

    Reply
    UVM
    #systemverilog #UVM

  7. Re: get_mirrored_value() mismatch

    Posted by Rahulkumar on Jan 9, 2020
    In reply to Bahaa Osman: mirror value of the register isn't updated until you read the register. To update the mirror values of all the registers same as their reset value, call the m_reg_model.reset() after dut reset or in reset phase. virtual task ...

    Reply
    UVM
    uvm_reg get_mirrored_value mirror

  8. Re: member technical staff

    Posted by Rahulkumar on Jan 9, 2020
    In reply to Rahul_nyol: Driver side: 1. get_next_item() is blocking call which gets sequence item and need to call the item_done() to complete the handshake before new item is requested using the get_next_item(). 2. get() is also a blocking call which get ...

    Reply
    UVM

  9. Re: what is the use of model.reset() method?

    Posted by Rahulkumar on Jan 7, 2020
    In reply to rag123: Quote: In reply to Rahulkumar Patel: Thanks Rahul. two questions (I am new to RAL) 1) where can i find more info on this? 2) How does the DUT registers and UVM RAL class hook up happen? 1) where can i find more info on this? There are ...

    Reply
    UVM

  10. Re: what is the use of model.reset() method?

    Posted by Rahulkumar on Jan 7, 2020
    In reply to rag123: Quote: what is the use of model.reset() method in uvm_reg_hw_reset_seq in RAL? I see based on the comments the sequence does the following. It calls model.reset() method, but i coudn't actually see how it actually drives the reset ...

    Reply
    UVM

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