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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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Ask a Question
UVM RAL
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  1. UVM_RAL::Linking Mirror models for a register accessible through two addresses on the same physical interface

    Posted by cdn on Apr 20, 2017
    UVM RAL Mirror Model uvm register w1c uvm register w1s We have a specific type of register in our design, which have two addresses to access the same physical register. When accessed through the first address, the behavior expected is W1S (Write one to se ...

    Question
    UVM
    RAL Mirror Model uvm register w1c uvm register w1s

  2. How to make some registers of DUT as not Accessible to the customer.

    Posted by shreemant.vats on Nov 14, 2016
    UVM RAL Advanced UVM Register RTL Cookbook: Registers/RegisterModelOverview Hello Dave, In Our DUT we don't want the customer to have access to certain registers, even though they are RW registers at the RTL level but customer should not be able to W ...

    Question
    UVM
    RAL Advanced UVM Register RTL Cookbook: Registers/RegisterModelOverview

  3. how to learn UVM RAL from basics?

    Posted by SV_UVM_Learner on Oct 4, 2016
    UVM RAL I know UVM.. I want to learn UVM RAL... What is the best way to learn UVM RAL from basics?? from which site/blog/book?? ...

    Question
    UVM
    RAL

  4. adapter class

    Posted by SV_UVM_Learner on Sep 28, 2016
    UVM RAL in adapter class, reg2bus method is having only one argument, while bus2reg method is having 2 arguments. why?? ...

    Question
    UVM
    RAL

  5. RAL frontdoor hang

    Posted by dipling on Aug 9, 2016
    UVM RAL fdsq timeout hang Hi, I am using RAL with a frontdoor sequence for accesses over JTAG. In one TC I am blocking the DUT queue on purpose and trigger a ral.jtag_read() expecting a timeout. After this point I am not able to use the frontdoor sequence ...

    Question
    UVM
    RAL fdsq timeout hang

  6. RAL

    Posted by Sivasankaran M on Aug 7, 2016
    UVM RAL I am using 2 register models. Both register model have been driven through same agent. And also both predictors bus_in in connected with monitor of the agent with two different analysis ports. Now, I am driving 2 sequences like in order of reg_mod ...

    Question
    UVM
    RAL

  7. uvm_reg_fifo broken?

    Posted by craigd on Aug 5, 2016
    UVM RAL uvm_reg_fifo Has anyone ever had a play with the uvm_reg_fifo? The implementation seems really broken. I was having issue similar to the ones here. So I started digging Basically, if you call FIFO.set() then FIFO.update(), then it gets itself into ...

    Question
    UVM
    RAL uvm_reg_fifo

  8. Backdoor access is not updating the register in the DUT

    Posted by Reuben on Jul 22, 2016
    UVM UVM_BACKDOOR RAL ral backdoor I setup a RAL in my testbench and I created a sequence to try the backdoor access. The sequence goes like this, virtual task body (); super.body ();   if (! tb_reg_block.reg_0. randomize ()) begin `uvm_fatal ("RAND_F ...

    Question
    UVM
    UVM_BACKDOOR RAL ral backdoor

  9. Confused about uvm_mem does not store memory content

    Posted by Reuben on Jul 19, 2016
    UVM uvm_mem RAL I'm reading the UVM RAL cookbook and I came to this section about uvm_mem. It says there that unlike uvm_reg, uvm_mem does not store the state or the memory content due to simulation overhead. From what I understand, it cannot store w ...

    Question
    UVM
    uvm_mem RAL

  10. Need logic for Burst read /write using RAL model

    Posted by vamsi.int@gmail.com on Jul 14, 2016
    UVM RAL BURST Hi, Have an issue regarding burst write/read through RAL model. Actually there is no option for Burst through RAL. But still my design requires burst write and read. How can I achieve it. ...

    Question
    UVM
    RAL BURST

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