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uvm check doubt

Posted by pkc431 on May 19, 2023
UVM #uvm #checks #monitor Hi, I have a payload which is 32 bits where i have different attributes like some tags, ids and length. The length is 4 i am trying to write a check where i want to see of one of the attributes is set to one, when it is set to on ...

Question
UVM

#uvm #checks #monitor
uvm_config_db get in UVM_object

Posted by verif_25 on May 18, 2023
UVM UVM Configuration database #UVM#configuration Hello, I am trying to retrieve information from my top testbench which is a parameter of my DUT, using set in the testbench and get in my agent_configuration file. so in my testbench I wrote this: uvm_conf ...

Question
UVM

UVM Configuration database #UVM#configuration
question on "pipelined access" in sequence- driver

Posted by puranik.sunil@tcs.com on May 18, 2023
UVM Hi, The UVM cookbook on page 266 states following regarding the pipelined accesses: " Pipelined Accesses Pipelined accesses are primarily used to stress test the bus but they require a different approach in the sequence. A pipelined sequence need ...

Question
UVM
UVM Ral Indirect Access

Posted by yang liu on May 18, 2023
UVM uvm ral indirect access I have a reg_block called A which has 2 indirect registers(address and data), I want to use these 2 indirect registers to access other reg_block's(B,C,D) registers, I saw uvm has this class: uvm_reg_indirect_data. I want t ...

Question
UVM

uvm ral indirect access
How can I create an array of agents of same type?

Posted by SharonBeaulah on May 17, 2023
UVM array of UVM agents I have to create a bunch of agents which are of same type. Can I create them as an array rather than copy pasting code again and again? ...

Question
UVM

array of UVM agents
Problem with.randomize "with"; why do the attribute names need to match?

Posted by jnbkeller on May 17, 2023
UVM randomize with constraint Hi everyone, thanks in advance for your help. I'm working with a 3rd party IP and am trying to randomize a transaction class. I get a runtime error as follows: # ** Fatal: Illegal unpacked assignment to type 'bit� ...

Question
UVM

randomize with constraint
Getting Clock period Mismatch Error while comparing two clocks even though values of two clocks are same

Posted by chakrik on May 17, 2023
UVM SV #Systemverilog #UVM #RAL clockcheck SV UVM clockcheck Hi All, I was trying to write clock checker, initially I calculated actual_period between two posedge of clocks and expected_period calculated from freequency, Im trying to calculate expected pe ...

Question
UVM

SV #Systemverilog #UVM #RAL clockcheck SV UVM clockcheck
How can we call function of DUT from testcase

Posted by irshad_mansur on May 17, 2023
UVM Backdoor_access HDL access methods Hi. I want to do something like this in my testcase top.dut.block_a.mem.do_backdoor_wr(); I am not able to do this as we can not do hierarchical access from package and all. Is there any alternative way for this? ...

Question
UVM

Backdoor_access HDL access methods
Built in methods to check if there are any register files in RAL

Posted by Prashanthp436 on May 15, 2023
UVM #RAL #UVM #PREDICTOR Hello. I have created a RAL model with the registers inside a register file as i wanted them to be replicated. May i know the details of the built in methods in RAL to check if RAL has register files and if so what are the registe ...

Question
UVM

#RAL #UVM #PREDICTOR
How to turn off Assertions?

Posted by A E Aravind on May 15, 2023
UVM Hi, I need to turnoff all the assertions from environment to all the below hierarchy agents and components. In my case, I have written like $assertoff(0,env.run_phase.assertion name) using this only that particular assertion will be turned off. But I ...

Question
UVM

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