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UVM RAL implementation methodology for large designs

Posted by rgarcia07 on Sep 6, 2019
UVM #uvm uvm_reg #UVM #RAL Hello, I was wondering if are there any resources (papers, blogs, posts) about methodologies to implement UVM RAL for "large" designs (>100K registers and 500K rams)? I tried to do some research online but most of t ...

Question
UVM

#uvm uvm_reg #UVM #RAL
SV Interface classes in UVM based environment

Posted by rgarcia07 on Jul 31, 2019
UVM #uvm #systemverilog multiple inheritance Hello, Is there any paper or example that uses SV interface classes in a UVM environment? I've seen some examples over the internet but none of them are "placed" in a UVM environment. Any pointer ...

Question
UVM

#uvm #systemverilog multiple inheritance
SystemVerilog Assertion for toggling signal

Posted by rgarcia07 on Jul 29, 2019
SystemVerilog #SVA systemverilog assertion concurrent SVA ASSERTION BASED VERIFICATION Hello, I'm trying to write a property to check a signal that behaves with the following requirements 1- signal 'a' should be high for a number of cycles ...

Question
SystemVerilog

#SVA systemverilog assertion concurrent SVA ASSERTION BASED VERIFICATION
Constraining/Selecting valid bins of a coverpoint using a queue or dynamic array

Posted by rgarcia07 on Jul 12, 2019
SystemVerilog coverpoint #coverage CrossQueueType Hello, I'm trying to restrict the bins of a coverpoint given by a queue or dynamic array something like this module tb (); bit [7: 0] addr; bit par; bit en = 0; // valid addresses to be covered bit ...

Question
SystemVerilog

coverpoint #coverage CrossQueueType
Random Stability

Posted by rgarcia07 on Feb 22, 2019
SystemVerilog random stability $random Hello, I've found in our testbench some code that uses $random to create some delay inside a module, I have read about random stability when creating objects and that you should use $urandom_range, std::random,. ...

Question
SystemVerilog

random stability $random
mixing types and operators in SystemVerilog

Posted by rgarcia07 on Jun 15, 2018
SystemVerilog operators Real datatypes Hello, I have a basic question about mixing datatypes and operators in SV, probably there is a section in the LRM but I'm not sure which could it be Let's say you have module test (); const int x = 10; cons ...

Question
SystemVerilog

operators Real datatypes
Communicating multiple producers to single consumer using mailbox

Posted by rgarcia07 on May 8, 2018
SystemVerilog mailbox Parameterized Components Hello, I've seen several examples of using mailboxes, to communicate between single producer and consumer "components", basically I can have a mailbox on each of them and then when connecting t ...

Question
SystemVerilog

mailbox Parameterized Components
SV transition coverage of non-contiguous values

Posted by rgarcia07 on Jan 18, 2017
Coverage #SystemVerilog #FunctionalCoverage Hello, While creating a covergroup (and coverpoint) using transition coverage I've encounter problem, For example you want to cover the following transition {2,4,7}-> {3,5,9}-> {2,4,7} If the values w ...

Question
Coverage

#SystemVerilog #FunctionalCoverage
UVM 1.1d reg write/read ordering

Posted by rgarcia07 on May 17, 2016
UVM Advanced UVM Register uvm uvm_reg Hello, I've been using the uvm_reg write/read operations, for 64-bit registers with a 32-bit interface (APB for example), I see that the write(), and read() tasks are able to send two bus accesses first lower-par ...

Question
UVM

Advanced UVM Register uvm uvm_reg
Is it possible to write Function Templates in SystemVerilog

Posted by rgarcia07 on Apr 12, 2016
SystemVerilog systemverilog Hello, Is it possible to write a function templates in SystemVerilog? I think in C++ you can do something like this template inline T const& Max (T const& a, T const& b) {return a < b? b:a;} ...

Question
SystemVerilog

systemverilog

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