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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

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      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • Static & Formal - Israel | May 31st
      • VA Live - Multiple Dates & Locations
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar
    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings
    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics
    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences
    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
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    • About Us

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    • Training

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Results

  1. UVM RAL implementation methodology for large designs

    Posted by rgarcia07 on Sep 6, 2019
    UVM #uvm uvm_reg #UVM #RAL Hello, I was wondering if are there any resources (papers, blogs, posts) about methodologies to implement UVM RAL for "large" designs (>100K registers and 500K rams)? I tried to do some research online but most of t ...

    Question
    UVM
    #uvm uvm_reg #UVM #RAL

  2. SV Interface classes in UVM based environment

    Posted by rgarcia07 on Jul 31, 2019
    UVM #uvm #systemverilog multiple inheritance Hello, Is there any paper or example that uses SV interface classes in a UVM environment? I've seen some examples over the internet but none of them are "placed" in a UVM environment. Any pointer ...

    Question
    UVM
    #uvm #systemverilog multiple inheritance

  3. SystemVerilog Assertion for toggling signal

    Posted by rgarcia07 on Jul 29, 2019
    SystemVerilog #SVA systemverilog assertion concurrent SVA ASSERTION BASED VERIFICATION Hello, I'm trying to write a property to check a signal that behaves with the following requirements 1- signal 'a' should be high for a number of cycles ...

    Question
    SystemVerilog
    #SVA systemverilog assertion concurrent SVA ASSERTION BASED VERIFICATION

  4. Constraining/Selecting valid bins of a coverpoint using a queue or dynamic array

    Posted by rgarcia07 on Jul 12, 2019
    SystemVerilog coverpoint #coverage CrossQueueType Hello, I'm trying to restrict the bins of a coverpoint given by a queue or dynamic array something like this module tb ();   bit [7: 0] addr; bit par; bit en = 0; // valid addresses to be covered bit ...

    Question
    SystemVerilog
    coverpoint #coverage CrossQueueType

  5. Random Stability

    Posted by rgarcia07 on Feb 22, 2019
    SystemVerilog random stability $random Hello, I've found in our testbench some code that uses $random to create some delay inside a module, I have read about random stability when creating objects and that you should use $urandom_range, std::random,. ...

    Question
    SystemVerilog
    random stability $random

  6. mixing types and operators in SystemVerilog

    Posted by rgarcia07 on Jun 15, 2018
    SystemVerilog operators Real datatypes Hello, I have a basic question about mixing datatypes and operators in SV, probably there is a section in the LRM but I'm not sure which could it be Let's say you have module test (); const int x = 10; cons ...

    Question
    SystemVerilog
    operators Real datatypes

  7. Communicating multiple producers to single consumer using mailbox

    Posted by rgarcia07 on May 8, 2018
    SystemVerilog mailbox Parameterized Components Hello, I've seen several examples of using mailboxes, to communicate between single producer and consumer "components", basically I can have a mailbox on each of them and then when connecting t ...

    Question
    SystemVerilog
    mailbox Parameterized Components

  8. SV transition coverage of non-contiguous values

    Posted by rgarcia07 on Jan 18, 2017
    Coverage #SystemVerilog #FunctionalCoverage Hello, While creating a covergroup (and coverpoint) using transition coverage I've encounter problem, For example you want to cover the following transition {2,4,7}-> {3,5,9}-> {2,4,7} If the values w ...

    Question
    Coverage
    #SystemVerilog #FunctionalCoverage

  9. UVM 1.1d reg write/read ordering

    Posted by rgarcia07 on May 17, 2016
    UVM Advanced UVM Register uvm uvm_reg Hello, I've been using the uvm_reg write/read operations, for 64-bit registers with a 32-bit interface (APB for example), I see that the write(), and read() tasks are able to send two bus accesses first lower-par ...

    Question
    UVM
    Advanced UVM Register uvm uvm_reg

  10. Is it possible to write Function Templates in SystemVerilog

    Posted by rgarcia07 on Apr 12, 2016
    SystemVerilog systemverilog Hello, Is it possible to write a function templates in SystemVerilog? I think in C++ you can do something like this template inline T const& Max (T const& a, T const& b) {return a < b? b:a;} ...

    Question
    SystemVerilog
    systemverilog

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