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Reading enum from a file

Posted by rag123 on Jan 15, 2022
UVM #uvm Hi, I am trying to read a enum from a file, but i dont see that is being driven from Sequence to driver and in the print statements. The example has read.txt which has 2 enum's and reading it from seq_a. Appreciate the help. Enum_from_file ...

Question
UVM

#uvm
Wait_for_item_done() is still in wait state even after item_done() is hit.

Posted by ganesh shetti on Dec 23, 2021
UVM #uvm #sequence wait_for_item_done item_done Hi, Following is the code snippet where i am getting the mentioned error. //test run_phase seq_lib.start(env.agent.sequencer); //sequence_lib task body for(i=0;i<4;i++) begin `uvm_create(tr); tr.randomize ...

Question
UVM

#uvm #sequence wait_for_item_done item_done
UVM ports are never registered with the factory, and covergroups are also never registered with the factory. Why?

Posted by Verif Engg on Dec 1, 2021
UVM #uvm UVM Factory Registration Hi All, This (http://www.sunburst-design.com/papers/CummingsSNUG2012SV_UVM_Factories.pdf) paper brings up a valid point: From the paper: "UVM ports are never registered with the factory, and covergroups are also neve ...

Question
UVM

#uvm UVM Factory Registration
Race condition between write() in UVM scoreboard

Posted by vignesh.kannan on Nov 26, 2021
UVM #monitor #uvm #UVM #scoreboard Assume there is a memory DUT whose interface signals are like: Rd interface: rden, rdaddr Wr interface: wren, wraddr, wdata If the DUT receives both wren and rden in the same clock cycle, it should service write first an ...

Question
UVM

#monitor #uvm #UVM #scoreboard
ACE Protocol Test bench Design

Posted by rag123 on Nov 25, 2021
UVM #uvm I am planning to write a ACE protocol UVM Test bench. Can somebody review this and see if it is okay? Also if somebody has written ACE protocol, can somebody share the test plan? 1) Have one ACE Interface 2) Master 1 and Master 2 are UVM componen ...

Question
UVM

#uvm
Expression on rhs is not a class or a compatible class and hence cannot be assigned to a class handle on lhs.

Posted by morslai on Nov 17, 2021
UVM #uvm #systemverilog #sequencer Hello everyone, I am trying to assign the sequencer from my agent to the sequencer in the environment and I get the next error: Expression on rhs is not a class or a compatible class and hence cannot be assigned to a cla ...

Question
UVM

#uvm #systemverilog #sequencer
What is std_logic_vector16(15 downto 0)?

Posted by bstephen on Nov 16, 2021
UVM VHDL #uvm #systemverilog I came across a VHDL DUT with two data types that I am unfamiliar with:: in std_logic_vector16 (15 downto 0);: in std_logic_vector32 (31 downto 0); Can someone explain what these data types are? Also, can std_logic_vector16 an ...

Question
UVM

VHDL #uvm #systemverilog
Why there is no procedural block or event scheduler in UVM?

Posted by venkata-srikanth on Nov 12, 2021
UVM #uvm #proceduralblock #eventschedular This is a question that I encountered in the process of learning UVM. I am a beginner in UVM so please try to be as basic as it's needed for this Question. ...

Question
UVM

#uvm #proceduralblock #eventschedular
Syntax Error on $cast

Posted by rag123 on Nov 3, 2021
UVM #uvm Can somebody tell me what is the problem with this syntax error? Link here ...

Question
UVM

#uvm
Example code of Single Master and Multi Slave or Multi Master Single Slave

Posted by rag123 on Oct 26, 2021
UVM #uvm Is there an code example of Single Master with Multi Slave or Multi Master with Single slave? Would like to see how the test bench and connection looks like. ...

Question
UVM

#uvm

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