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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

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      • Introduction to ISO 26262
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      • Assertion-Based Verification
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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    • Coverage Cookbook

      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • U2U MARLUG - January 26th
      • Creating an Optimal Safety Architecture  - February 9th
      • The ABC of Formal Verification - February 11th
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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  1. Re: Pass variable from test to sequence

    Posted by Rahulkumar on Jan 22, 2020
    In reply to harshavs: //It can be done without using config db class test extend base_test;   task run_phase   seq1. start (); //uvm_config_db #(bit [6:0])::set(this,"*","var",seq1.var);   seq2. var = seq1. var; // OR ser2.randomize() ...

    Reply
    UVM

  2. Re: Driver- RUN phase without get_next_item()

    Posted by Rahulkumar on Jan 21, 2020
    In reply to chr_sue: Quote: In reply to Rahulkumar: It is useless what you are doing. Look at the simulation log-file. You have always the same data. This is because you are doing the randomization in the constructor of the driver. This is the wrong place ...

    Reply
    UVM
    Driver RUN phase not started

  3. Re: Delay between driver driving the interface signals and monitor sampling the same

    Posted by Rahulkumar on Jan 20, 2020
    In reply to tpan: Quote: In reply to Rahulkumar: I get your point. But I remember seeing simulations where the timestamps at the point the data is sampled by monitor matches the timestamp when the data is driven (while looking at the waveform). How do you ...

    Reply
    UVM

  4. Re: Driver- RUN phase without get_next_item()

    Posted by Rahulkumar on Jan 20, 2020
    In reply to J_M: you can directly pass the drive class using run_test() or create test case and instantiate the driver. Fixed few issues, https://www.edaplayground.com/x/4pRH ...

    Reply
    UVM
    Driver RUN phase not started

  5. Re: Exiting a sequence that has a forever loop

    Posted by Rahulkumar on Jan 18, 2020
    In reply to chr_sue: Quote: In reply to Rahulkumar: But, if your sequences have all forever loops no one will stop! Yes, i agree with you at least one sequence should finish. ...

    Reply
    UVM

  6. Re: Exiting a sequence that has a forever loop

    Posted by Rahulkumar on Jan 18, 2020
    In reply to chr_sue: Quote: In reply to tpan: Quote: In reply to Rahulkumar: Thanks Rahulkumar. I will try with fork-join_any. I think that might work The fork/join_any will not stop the executung unless you have at least 1 sequence without a forever loop ...

    Reply
    UVM

  7. Re: Delay between driver driving the interface signals and monitor sampling the same

    Posted by Rahulkumar on Jan 17, 2020
    In reply to tpan: Quote: In reply to Rahulkumar: So is this what all testbenches see, that is driving of data happens at clk_cycle T and this data is shown as being sampled by the monitor at clk_cycle T+1. No, it's depend on your requirement. 1. You ...

    Reply
    UVM

  8. Re: Exiting a sequence that has a forever loop

    Posted by Rahulkumar on Jan 17, 2020
    In reply to tpan: you need to drop the objections to stop the simulation. virtual task main_phase (uvm_phase phase); super.main_phase (phase); phase.raise_objection (this, "raise objection"); //raise objection   fork begin /* //infinite sequence ...

    Reply
    UVM

  9. Re: Setting a sequence item Param from another sequence

    Posted by Rahulkumar on Jan 16, 2020
    In reply to UVM_learner6: It should work. I hope width of data is sufficient to hold the a*b. For example, a,b are 32 bit then data should be at least 64bit(data=a*b). This is just an example code. Please check variables width in your code. class myPacket ...

    Reply
    UVM

  10. Re: Declaring a uvm_report_server class

    Posted by Rahulkumar on Jan 16, 2020
    In reply to tpan: Quote: Thanks Dave. It's an interesting feature that you pointed out here. I have used UVM quite a bit but never realized it. I guess I have always had my variables declared globally in the class. So am I right in saying that even t ...

    Reply
    UVM

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