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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

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Ask a Question
UVM RAL
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  1. UVM_RAL Frontdoor methods

    Posted by abhishek403 on Apr 24, 2018
    UVM frontdoor backdoor RAL uvm_reg_sequence Hi, Actually I was doing UVM_RAL. can anyone help me out from these 4 doubts. 1. what is the exact difference between uvm_reg_sequence and uvm_sequence #(uvm_sequence_item) in frontdoor access..? 2. what is the ...

    Question
    UVM
    frontdoor backdoor RAL uvm_reg_sequence

  2. RAL- clear on read registers

    Posted by verif_learner on Apr 18, 2018
    UVM RAL I am describing IP-XACT definition for a DUT. The DUT has several registers that clear on read (example, interrupt status). I see that IP-XACT does not provide any option to capture this type of register. How is this to be handled? ...

    Question
    UVM
    RAL

  3. RAL: uvm_reg_map base address does not work

    Posted by Mohamed_TN on Mar 5, 2018
    UVM uvm_reg_map uvm_reg_block m_base_addr RAL Hello, I'm trying to set a base address of the default_map different from 0 using the the create_map function as the following: this.default_map = create_map ("", 3 2'h00010000, 4, UVM_LITT ...

    Question
    UVM
    uvm_reg_map uvm_reg_block m_base_addr RAL

  4. UVM RAL LIBRARY BUG OR

    Posted by maxiale on Feb 28, 2018
    UVM UVM RAL CHECK_ON_READ DO_CHECK Hey guys! I'm faced with problem in UVM RAL working with "byte enable interface". Prelude. So let's assume that we have 32bit AHB bus and we want to execute halfword read access to slave with addr enc ...

    Question
    UVM
    UVM RAL CHECK_ON_READ DO_CHECK

  5. How to set_compare(UVM_NO_CHECK) to individual bits of register fields?

    Posted by shahkavish77 on Feb 27, 2018
    UVM UVM_NO_CHECK set_compare bit_access backdoor_check RAL Hi, I am having one Register defined with some fields. 32-bits wide Register R1 with fields F1, F2, F3, F4- each 8 bits wide. Now for backdoor check, I want to set UVM_NO_CHECK for bit 0 of R1, me ...

    Question
    UVM
    UVM_NO_CHECK set_compare bit_access backdoor_check RAL

  6. UVM RAL, PIPELINE, BACK TO BACK

    Posted by maxiale on Feb 12, 2018
    UVM back2back AHB RAL Pipelined Hey! I'm interested ways to solve problem with pipeline interface (AHB-like). I want to use regmodel with access registers in back-2-back way. Maybe you know some papers about that? At first sight it's not trivial ...

    Question
    UVM
    back2back AHB RAL Pipelined

  7. How to update the mirror value of register.

    Posted by murali405 on Feb 8, 2018
    UVM RAL register read() mirror set_check_on_read mirrored value Mirrored values and desired values in UVM RAL Hi, I got stuck with the updating mirrored value of RO register in RAL. I have a Read only register "status" in the RTL. and i have RAL ...

    Question
    UVM
    RAL register read() mirror set_check_on_read mirrored value Mirrored values and desired values in UVM RAL

  8. Register Addressing RAL

    Posted by t.sukanthi on Sep 8, 2017
    UVM RAL Advanced UVM Register I already have a working UVM RegModel built for an IP (class IP_regmodel) Now I have to instantiate this IP two times in my Testbench. How can I extend this RegModel now? Because the register addresses for both the IPs are th ...

    Question
    UVM
    RAL Advanced UVM Register

  9. Broadcast register read/write with RAL

    Posted by Vperrin on Sep 7, 2017
    UVM RAL Advanced UVM Register UVM callback Hi all, recently I had to deal with following broadcast scenario. I have one register block tx_reg_block and one rx_reg_block. In top_tx_block I have 4 instances of tx_reg_block and in top_rx_block I have 4 insta ...

    Question
    UVM
    RAL Advanced UVM Register UVM callback

  10. Changing sequemcer handle in reg_seqs still triggers register writes

    Posted by msuthar on May 14, 2017
    UVM RAL HEllo ALl, I am facing a unique problem. I have a RAL implemented and register sequence which works on I2C and have I2C driver, transaction and sequencer respectively. Now once i made a typo while declaring the sequencer for my reg sequence as fol ...

    Question
    UVM
    RAL

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