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Interview Questions on UVM

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog I faced conflict to answer for the below Queries in interview,Please give knowledge in the below listed Queries: 1. don’t want to register a sequence to sequencer. What is the alternate macro to uvm_sequence_utils() macro? 2. For d ...

Question
UVM

#uvm #systemverilog
How driver will request each time to sequencer or sequence need different sequence_item on same interface

Posted by Subbi Reddy on Nov 26, 2020
UVM #uvm #systemverilog How driver will request each time to sequencer or sequence need different sequence_item on same interface ...

Question
UVM

#uvm #systemverilog
How to run multiple testcases in single run?

Posted by Manirama on Nov 25, 2020
UVM #uvm The below link can be used to run any one testcase at time (write_test or read_test or mem_wr_rd_test wr_rd_test). how to run all testcases at a time. https://www.edaplayground.com/x/2arP Please help. ...

Question
UVM

#uvm
Using uvm_config_db in sequence

Posted by UVM_SV_101 on Nov 19, 2020
UVM #uvm #uvm_config_db Hi, I am curious to know how uvm_config_db works to send item from component class to object class. Since component and object class have no visibility to each others hierarchy, how does set-get method work across the classes? I tr ...

Question
UVM

#uvm #uvm_config_db
Where to place sample_values() for getting coverage in UVM RAL?

Posted by Keiichi McGuire on Nov 17, 2020
UVM #uvm #UVM #RAL As a brute force method, I can call sample_values() inside an always block @(posedge clk). However, this is not very performance efficient. I'm not quite clear on how a RAL's built in write()/read() API call goes through, but ...

Question
UVM

#uvm #UVM #RAL
Unable to compile a register model using registers of size 2048 bits

Posted by Marc43 on Nov 15, 2020
UVM UVM Questa questasim #uvm uvm register model Hello, I am unable to compile my register model using registers of size 2048 bits. I know that the default size is 64 and we have to do +define+UVM_REG_DATA_WIDTH=2048 when compiling UVM. But it doesn' ...

Question
UVM

UVM Questa questasim #uvm uvm register model
DUT Speed calculation

Posted by Subbi Reddy on Nov 13, 2020
UVM #uvm How to Know Input and output Speed of the DUT?? ...

Question
UVM

#uvm
Backdoor access to memory issue

Posted by Lukas102 on Nov 12, 2020
UVM #uvm Hello, I have an issue related with backdoor access to memory i.e. path appears to be fine, also +acc visibility is turned on, however the access throws an error: # UVM_ERROR: Unable to read value from 'dut_top.dut_wrapper.dut.module_path.me ...

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UVM

#uvm
the PCIe test do not completed sometimes, phase stucks

Posted by Levard on Nov 6, 2020
UVM #uvm Hello everyone! Now I work with my former colleague's PCIe with PHY VIP environment. I rewrote a sequence with asserting and deasserting interrupts. Some tests (with some seeds) are completed successfully PCIE INFO-- (uvm_phase.svh: 1345) [P ...

Question
UVM

#uvm
how to change RTL signals during the simulation in the testbench

Posted by zz8318 on Nov 3, 2020
UVM #uvm #verilog #testbench I'd like to ask a question how to change RTL signals during the simulation in our TB? Usually we will force some of signals (most of them are input for our DUT) in the top like below. module top;... initial begin force tb ...

Question
UVM

#uvm #verilog #testbench

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