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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
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    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
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      • FPGA Verification
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    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
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      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • Static & Formal - Israel | May 31st
      • VA Live - Multiple Dates & Locations
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar

    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings

    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics

    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences

    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification IQ
      • Verification Horizons Blog
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
      • Verification Horizons - July 2022
      • Issue Archive

    • About Us

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    • Training

      • Learning @OneGlance (PDF)
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Ask a Question
UVM
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  1. UVM driver sequencer interaction with parameterized sequence item

    Posted by Brass on May 24, 2023
    UVM uvm driver sequencer interaction parameterized sequence item I have a sequence item of the type: class seq_item # (int PARAM_NAME) extends uvm_sequence_item; `uvm_object_param_utils (seq_item # (PARAM_NAME)) The sequence item is created in the sequenc ...

    Question
    UVM
    uvm driver sequencer interaction parameterized sequence item

  2. In OOO scoreboard example and need_to_compare

    Posted by wyc123 on May 24, 2023
    UVM #UVM #scoreboard In the OOO scoreboard example, "need_to_compare"is assigned from below code: need_to_compare = (rcv_count.exists (idx) && ((is_before && rcv_count [idx] > 0) || (! is_before && rcv_count [idx] < ...

    Question
    UVM
    #UVM #scoreboard

  3. Enable checks in post simulation phase if simulation phase is clean

    Posted by sahith on May 24, 2023
    UVM #UVM #ERRORS #CHECKS Hi, I want to enable some checks in the post simulation phase like check/final phase but, I want to enable it only if simulation phase has no uvm_errors. Thanks, Sahith ...

    Question
    UVM
    #UVM #ERRORS #CHECKS

  4. Info regarding built in sequences for memory

    Posted by Prashanthp436 on May 23, 2023
    UVM #RAL Hello. I need clarification regarding the usage of built in sequences in RAL to verify memories in DUT. For registers, write and read methods will write and read from DUT and compares against mirrored values in RAL(Mentioned in write and read API ...

    Question
    UVM
    #RAL

  5. How to redefine interface parameters [UVM PARAMETERIZED INTERFACE]

    Posted by verif_25 on May 23, 2023
    UVM #UVM #Parameter #virtual_interface #System verilog #interface #uvm #parameterized_interface Hello I have the following issue related to the redefinition of interface parameters. Actually, I have a design with multiples parameters. so basically I have ...

    Question
    UVM
    #UVM #Parameter #virtual_interface #System verilog #interface #uvm #parameterized_interface

  6. Reads from AHB Slave VIP to APB Master VIP

    Posted by ArulD on May 23, 2023
    UVM Hello, Apologies if my question is very basic one. Thanks in advance for your help! I am wondering how to acheive this particular UVM implementation. I have a DUT with AHB master port & APB slave port. I have connected AHB Slave VIP & APB Mast ...

    Question
    UVM

  7. customizing UVMF scoreboard

    Posted by Moein75 on May 22, 2023
    UVM #scoreboard #UVMF In the UVMF base scoreboard, dut outputs and predictor outputs are compared in order. But it is not deterministic when the design output is valid. In other words, the outputs of the dut after a while are the same as the outputs of th ...

    Question
    UVM
    #scoreboard #UVMF

  8. Questions on Lock() a sequencer

    Posted by vbabusr on May 21, 2023
    UVM Hi, I was trying to understand the difference between grab() vs lock(). The page below says https://verificationacademy.com/cookbook/sequences/lockgrab The sequencer lock method is called from a sequence and its effect is that the calling sequence wil ...

    Question
    UVM

  9. factory type override of sequence item does not work

    Posted by UVM_LOVE on May 20, 2023
    UVM #uvm #factory #override Hi, Can Factory override the uvm_sequence_item? Following code does not override the sequence item type used by the driver class. set_type_override_by_type(mem_seq_item::get_type(), child_seq_item::get_type()); I can't get ...

    Question
    UVM
    #uvm #factory #override

  10. Overwriting Assign statement

    Posted by Abdelrahman Adel on May 19, 2023
    UVM I have an assignment statement that assigns an enum variable of type logic defined in an interface in my top module, when I overwrite this variable in the body task of my sequence (which is supposed to be a procedural code) there is no compilation err ...

    Question
    UVM

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