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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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      • Planning, Measurement, and Analysis
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
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      • UVM Connect
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      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
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      • Start Here - Patterns Library Overview
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
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      • Register Abstraction Layer
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    • Coding Guidelines & Deployment

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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • VA Live - Multiple Dates & Locations
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    • On-Demand Library

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      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
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      • All On-Demand Recordings

    • Recording Archive

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      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics

    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
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      • Industry Data & Surveys
      • DVCon 2023
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    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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Ask a Question
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Results

  1. Process vs Thread

    Posted by Jung Ik Moon on Jun 6, 2023
    SystemVerilog #systemverilog process thread Hi, In the context of SystemVerilog, is there a difference between the terms 'process' and 'thread'? LRM seems to use both of these terms (for example when describing a fork-join block). Are ...

    Question
    SystemVerilog
    #systemverilog process thread

  2. uvm_config_db and the mysterious build phase group

    Posted by wajahatriaz on Jun 6, 2023
    UVM #uvm #uvm_config_db #get_full_name() I have various issues with the following code example. I have explicitly used the methods of uvm_config_db class in separate phases because the get method blocks and the $display statements after it are not execute ...

    Question
    UVM
    #uvm #uvm_config_db #get_full_name()

  3. SV Assertion

    Posted by new_to_uvm on Jun 5, 2023
    SystemVerilog How do I write a property for the following:- When signal aa toggles from 0 to 1, signal bb should become 1'b0 after 5 ns and should remain 1'b0 till signal aa = 1. Note that signal aa is an asynchronous input. Thanks! ...

    Question
    SystemVerilog

  4. Flexible interface that supports scaler or arrays

    Posted by jnbkeller on Jun 5, 2023
    SystemVerilog interface array type mismatch Hi all, Thanks in advance for any suggestions. I'm presenting a conceptual example showing how I'd like to make an interface re-usable when connecting to a DUT with different data types. I'm tryin ...

    Question
    SystemVerilog
    interface array type mismatch

  5. Parameterized Classes

    Posted by zhon1231 on Jun 5, 2023
    UVM Hi all, I am in the middle of writing a parametrized class, and I hit a road block. Is there a way I can overwrite a parameter in the type_id::create call? For example, can I do something similar to this? Class A #(int j=10).... endclass Class B A m_a ...

    Question
    UVM

  6. can we use interface in object in uvm?

    Posted by lalithjithan on Jun 5, 2023
    UVM can we use interface in objects in uvm? ...

    Question
    UVM

  7. Cast parameterizable class whose parameter is extended from the other

    Posted by Martin Velay on Jun 5, 2023
    UVM #uvm #parameter #polymorphism Hi all, I am trying to make a kind of reusable UVM scoreboard but I have an issue to connect my analysis ports from my monitor to my scoreboard. This connection attempt is made in my environment. Here below you may find a ...

    Question
    UVM
    #uvm #parameter #polymorphism

  8. $floor (-4/3) yields-1 instead of-2

    Posted by Srini @ CVCblr.com on Jun 5, 2023
    SystemVerilog A related but not the same (mod) function: module m;   initial begin $display ("FL: 4/3 %0d", $floor (4 / 3)); $display ("FL:-4/3 %f", $floor (- 4 / 3)); end endmodule Tools give me-1, whereas C/PY/Matlab give-2. As per L ...

    Question
    SystemVerilog

  9. Using ** operator for restricting for loop in SystemVerilog

    Posted by blaze09 on Jun 4, 2023
    SystemVerilog I am trying to generate a parameterizable CSA tree. I am wondering if this for loop will work as intended: generate for (x = 1; x < DATA_LEN_CLOG; x ++) begin for (int j = 0; j < (DATA_LEN / (2 ** x)) / 2; j ++) begin <--- For loop ...

    Question
    SystemVerilog

  10. Using Ternary operator in SVA for Temporal scenario

    Posted by MICRO_91 on Jun 3, 2023
    SystemVerilog Using Ternary operator in SVA for Temporal scenario Hi All, A recent thread invoked interest whether ternary operator can replace if- else. The example in the thread has consequent in non-temporal context. I was wondering if ternary operator ...

    Question
    SystemVerilog
    Using Ternary operator in SVA for Temporal scenario

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