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Compensating for different timeunits between SystemVerilog packages

Posted by Paul McKechnie on Aug 27, 2018
SystemVerilog begin_tr end_tr timeunit I am performing transaction recording in a custom UVM monitor, where the agent has a different timeunit to the rest of the test bench. When I measure the current simulation time, the $time system call correctly repor ...

Question
SystemVerilog

begin_tr end_tr timeunit
If timeunit and timeprecision declaration is mandatory with a value which is power of 10 units?

Posted by psubudhi on Sep 13, 2017
SystemVerilog #systemverilog delay timescale timeunit systemverilog timeunit SV LRM says that, Section 18.10: Time unit and precision Use of these declarations removes the file order dependencies problems with compiler directives. The time unit and precis ...

Question
SystemVerilog

#systemverilog delay timescale timeunit systemverilog timeunit
clock period absolute time

Posted by alexkidd84 on Jun 11, 2017
SystemVerilog clock Timescale issue timeunit Period Is there a way to get the clock period in absolute time (i meain in terms of seconds)? For example I have a realtime 6.4ns clock period (and timeunit is 1ns). Ho can I get this value in seconds? Alessand ...

Question
SystemVerilog

clock Timescale issue timeunit Period
Declaring timeunit in package

Posted by eoss on Aug 11, 2014
SystemVerilog Package import timeunit Good day. I declare period of my clock frequensy in a package, and that's where i define timeunit, my code looks like this: package Clock_pkg; timeunit 100ps; timeprecision 1 ps; parameter Period = 156; endpackag ...

Question
SystemVerilog

Package import timeunit