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variable delay in property assertion

Posted by govind mualagapaka on Sep 21, 2019
UVM can you tell give write variable delay in property hi property variable_delay(counter); @ (negedge clk) disable iff(rst_n!== 1'b1) (data[35] == 1'b1 && data[34] == 1'b0 && error[5:0] == 6'b000000) |-> ##[50:150] ...

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UVM

can you tell give write variable delay in property
Re: variable delay in property assertion

Posted by chr_sue on Sep 21, 2019
In reply to govind mualagapaka: The range can be specified with data which are fix during elaboration time, i.e. variables cannot be used. But it lookss like you have a desgn problem. The range you are currently using is quite big. Does your design really ...

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UVM

can you tell give write variable delay in property
Re: How do I connect to uvm_reg type for UVM register test?

Posted by chr_sue on Sep 21, 2019
In reply to UVM_LOVE: In the run task of your test you aremissing this line: reg_model.get_registers (regs); ...

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UVM

uvm uvm_reg
How do I connect to uvm_reg type for UVM register test?

Posted by UVM_LOVE on Sep 21, 2019
UVM uvm uvm_reg Dear All, Now I'm trying to understand a UVM Register test method. Once to know it, I make a simple register model and test class as the below. // Code your testbench here // or browse Examples module test (); import uvm_pkg::*; `incl ...

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UVM

uvm uvm_reg
can inject error/fault in driver without seq_item indicating it?

Posted by uvmsd on Sep 21, 2019
UVM fault injection I have a testbench, where in cs(chip_select) is generated in the uvm driver. TB needs to send serial data to RTL and follows SPI interace protocol. UVM TB sends a fixed number of bytes of data to RTL(as per the requirement specificatio ...

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UVM

fault injection
Use of delayed crc in ethernet

Posted by SATYA369 on Sep 21, 2019
Downloads Ethernet What is the use of dly_crc_en bit in ethernet?How it works? Thanks SATYA ...

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Downloads

Ethernet
How to get handle to env from the sequence in uvm?

Posted by shilpak1 on Sep 20, 2019
UVM How to get handle to env from the sequence in uvm? ...

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UVM
Re: How to get handle to env from the sequence in uvm?

Posted by chr_sue on Sep 20, 2019
In reply to Leo Lian: Quote: In reply to chr_sue: But why not? Would you provide a better solution to deal with the problem I mentioned above? What you want to do is a bad approach because it is limiting your project data for re-use. There are tons of bet ...

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UVM
When master signal is asserted a slave signal should be asserted after some time delay. the assertion is not failing if the duration is more

Posted by srirahulch95 on Sep 20, 2019
SystemVerilog #SVA Assertions SV property p_max_time(clk,master_rise,slave_rise,duration); time start_time; @(posedge clk) ($rose(master_rise),start_time = $time) |-> [*0:$] $rose(slave_rise) ##0 (($time-start_time) == duration); endproperty assert pro ...

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SystemVerilog

#SVA Assertions SV
Re: When master signal is asserted a slave signal should be asserted after some time delay. the assertion is not failing if the duration is more

Posted by mbhat on Sep 20, 2019
In reply to ben@SystemVerilog.us: Hi Ben, I totally agree to this. I did not think in that perspective. Thank you. ...

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SystemVerilog

#SVA Assertions SV

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