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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

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    • Featured Courses

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      • Power Aware Verification
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    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
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      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
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  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

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      • UVM Basics
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
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      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Web Seminar: Clock-Domain Crossing Analyses and Verification - June 27th
      • Web Seminar: Accelerate Design-to-revenue in ASIC Developments - July 10th
      • Low Power Verification Forum
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    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
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    • Mentor Training Center

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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Ask a Question
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Forum Search

Results

  1. Re: Infinite loop due to signed arithmetic

    Posted by dave_59 on Jun 24, 2019
    In reply to prashantg: You either declare offset as signed, or use a separate signed loop variable. for (int loop = 'h1000- 'h4; loopt >= 'h0000; loop-= 'h4) begin offset = loop; ...

    Reply
    SystemVerilog
    SystemVerilog signed arithmetic

  2. Infinite loop due to signed arithmetic

    Posted by prashantg on Jun 24, 2019
    SystemVerilog SystemVerilog signed arithmetic I have the following piece of code, which is leading to an infinite loop due to comparison issue: bit [23: 0] offset; for (offset = 'h1000- 'h4; offset >= 'h0000; offset-= 'h4) begin Wha ...

    Question
    SystemVerilog
    SystemVerilog signed arithmetic

  3. Killing sequence error: [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer

    Posted by Mohamed_TN on Jun 24, 2019
    UVM #uvm #killing_sequence #SEQREQZMB Hi, could somebody tells me how can I bypass the following uvm_error when I'm trying to kill a running sequence before getting ended normally, UVM reports the following error: uvm_test_top.env.ahb_system_env.mast ...

    Question
    UVM
    #uvm #killing_sequence #SEQREQZMB

  4. Re: Killing sequence error: [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer

    Posted by dave_59 on Jun 24, 2019
    In reply to Mohamed_TN: Perhaps these articles on On-the-Fly reset could help. They're old, but may be still might be relevant. http://verificationhorizons.verificationacademy.com/volume-8_issue-2/articles/stream/on-the-fly-reset_vh-v8-i2.pdf https:/ ...

    Reply
    UVM
    #uvm #killing_sequence #SEQREQZMB

  5. Web Seminar Notification: Clock-Domain Crossing (CDC) Analyses and Verification

    Posted by Administrator on Jun 24, 2019
    Announcements Web Seminar Questa CDC Clock-Domain Crossing Verification Metastability Are you a Design or Verification Engineer or Manager interested in CDC Verification? This web seminar explains the importance of a complete CDC methodology to produce er ...

    Question
    Announcements
    Web Seminar Questa CDC Clock-Domain Crossing Verification Metastability

  6. Effect of clocking block skew on combinational logic

    Posted by uvmsd on Jun 24, 2019
    UVM clocking block: UVM TB I updated my UVM TB for up_down_counter for clocking block and I see below issue with non-zero skew value: RTL code is: module up_down_counter (input clk, input run_counter, // clk_en input rst_n, // Asynchronous reset active lo ...

    Question
    UVM
    clocking block: UVM TB

  7. Re: Killing sequence error: [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer

    Posted by chr_sue on Jun 24, 2019
    In reply to Mohamed_TN: Your sequence should never have a connection to the virtual interface. which tydata type is the avort variable? Is it an event or what is it? ...

    Reply
    UVM
    #uvm #killing_sequence #SEQREQZMB

  8. Re: Killing sequence error: [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer

    Posted by Mohamed_TN on Jun 24, 2019
    In reply to chr_sue: 1) I just put it to simplify but it can be anything come from virtual interface or anywhere in the environment 2) yes ...

    Reply
    UVM
    #uvm #killing_sequence #SEQREQZMB

  9. Re: Killing sequence error: [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer

    Posted by chr_sue on Jun 24, 2019
    In reply to Mohamed_TN: 2 questions: (1) where d9oes the abort variable does come from? (2) your vip1_seq is running forever togetzerr with your reg_seq in a fork/join_any. Is this your intention? ...

    Reply
    UVM
    #uvm #killing_sequence #SEQREQZMB

  10. Re: Infinite loop due to signed arithmetic

    Posted by prashantg on Jun 24, 2019
    In reply to dave_59: Dave, looks like I made a serious typo. Can you have a look again? ...

    Reply
    SystemVerilog
    SystemVerilog signed arithmetic

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