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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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Results

  1. Process vs Thread

    Posted by Jung Ik Moon on Jun 6, 2023
    SystemVerilog #systemverilog process thread Hi, In the context of SystemVerilog, is there a difference between the terms 'process' and 'thread'? LRM seems to use both of these terms (for example when describing a fork-join block). Are ...

    Question
    SystemVerilog
    #systemverilog process thread

  2. Re: Process vs Thread

    Posted by Robert.Lanier on Jun 6, 2023
    In reply to dave_59: Hi Dave, The issue of proper use of threads and fork/join statements seems to always get me wrapped around the axle. Can you recommend a good reference paper (preferred) or conference proceedings on this subject? For that matter, if y ...

    Reply
    SystemVerilog
    #systemverilog process thread

  3. factory type override of sequence item does not work

    Posted by UVM_LOVE on Jun 6, 2023
    UVM #uvm #factory #override Hi, Can Factory override the uvm_sequence_item? Following code does not override the sequence item type used by the driver class. set_type_override_by_type(mem_seq_item::get_type(), child_seq_item::get_type()); I can't get ...

    Question
    UVM
    #uvm #factory #override

  4. Re: factory type override of sequence item does not work

    Posted by ABD_91 on Jun 6, 2023
    In reply to chrisspear: Quote: Where do things stand now? Does the testbench compile and simulate? We have provided our inputs, I think this is for the user to check and confirm. ...

    Reply
    UVM
    #uvm #factory #override

  5. uvm_config_db and the mysterious build phase group

    Posted by wajahatriaz on Jun 6, 2023
    UVM #uvm #uvm_config_db #get_full_name() I have various issues with the following code example. I have explicitly used the methods of uvm_config_db class in separate phases because the get method blocks and the $display statements after it are not execute ...

    Question
    UVM
    #uvm #uvm_config_db #get_full_name()

  6. Re: uvm_config_db and the mysterious build phase group

    Posted by MICRO_91 on Jun 6, 2023
    In reply to wajahatriaz: If you insist on using build_phase() for animal, here is an alternative to Dave' solution: animal_h1 = animal:: type_id:: create ("zanimal_h1", null); // First letter should be between "v" and "z" ...

    Reply
    UVM
    #uvm #uvm_config_db #get_full_name()

  7. Cross SVA of multiple interfaces

    Posted by michi_g on Jun 5, 2023
    UVM UVM uvm sva I have two systemverilog interfaces to interact with my DUT and I defined systemverilog assertions in both to verify timing. Now I'll need to write assertions involving signals of both interfaces. How would I integrate this into my UV ...

    Question
    UVM
    UVM uvm sva

  8. Re: uvm_config_db and the mysterious build phase group

    Posted by wajahatriaz on Jun 5, 2023
    In reply to dave_59: Dave, I agree with what you stated and it solved my problem and now I'm able to grasp it. I still have another query. As you stated that the build_phase never gets executed, but why do the other phases work? In my example, I have ...

    Reply
    UVM
    #uvm #uvm_config_db #get_full_name()

  9. Re: uvm_config_db and the mysterious build phase group

    Posted by wajahatriaz on Jun 5, 2023
    In reply to dave_59: Thanks again Dave:) ...

    Reply
    UVM
    #uvm #uvm_config_db #get_full_name()

  10. Re: SV Assertion

    Posted by ben@SystemVerilog.us on Jun 5, 2023
    In reply to new_to_uvm: Try something like the following: Keep in mind that task t_aabb() is forked at every @(posedge aa), thus, the 2n posedge of aa will triggered it again. with a guard for a single trigger of the task https://www.edaplayground.com/x/H ...

    Reply
    SystemVerilog

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