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Process vs Thread

Posted by Jung Ik Moon on Jun 6, 2023
SystemVerilog #systemverilog process thread Hi, In the context of SystemVerilog, is there a difference between the terms 'process' and 'thread'? LRM seems to use both of these terms (for example when describing a fork-join block). Are ...

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SystemVerilog

#systemverilog process thread
Re: Process vs Thread

Posted by Robert.Lanier on Jun 6, 2023
In reply to dave_59: Hi Dave, The issue of proper use of threads and fork/join statements seems to always get me wrapped around the axle. Can you recommend a good reference paper (preferred) or conference proceedings on this subject? For that matter, if y ...

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SystemVerilog

#systemverilog process thread
factory type override of sequence item does not work

Posted by UVM_LOVE on Jun 6, 2023
UVM #uvm #factory #override Hi, Can Factory override the uvm_sequence_item? Following code does not override the sequence item type used by the driver class. set_type_override_by_type(mem_seq_item::get_type(), child_seq_item::get_type()); I can't get ...

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UVM

#uvm #factory #override
Re: factory type override of sequence item does not work

Posted by ABD_91 on Jun 6, 2023
In reply to chrisspear: Quote: Where do things stand now? Does the testbench compile and simulate? We have provided our inputs, I think this is for the user to check and confirm. ...

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UVM

#uvm #factory #override
uvm_config_db and the mysterious build phase group

Posted by wajahatriaz on Jun 6, 2023
UVM #uvm #uvm_config_db #get_full_name() I have various issues with the following code example. I have explicitly used the methods of uvm_config_db class in separate phases because the get method blocks and the $display statements after it are not execute ...

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UVM

#uvm #uvm_config_db #get_full_name()
Re: uvm_config_db and the mysterious build phase group

Posted by MICRO_91 on Jun 6, 2023
In reply to wajahatriaz: If you insist on using build_phase() for animal, here is an alternative to Dave' solution: animal_h1 = animal:: type_id:: create ("zanimal_h1", null); // First letter should be between "v" and "z" ...

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UVM

#uvm #uvm_config_db #get_full_name()
Cross SVA of multiple interfaces

Posted by michi_g on Jun 5, 2023
UVM UVM uvm sva I have two systemverilog interfaces to interact with my DUT and I defined systemverilog assertions in both to verify timing. Now I'll need to write assertions involving signals of both interfaces. How would I integrate this into my UV ...

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UVM

UVM uvm sva
Re: uvm_config_db and the mysterious build phase group

Posted by wajahatriaz on Jun 5, 2023
In reply to dave_59: Dave, I agree with what you stated and it solved my problem and now I'm able to grasp it. I still have another query. As you stated that the build_phase never gets executed, but why do the other phases work? In my example, I have ...

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UVM

#uvm #uvm_config_db #get_full_name()
Re: uvm_config_db and the mysterious build phase group

Posted by wajahatriaz on Jun 5, 2023
In reply to dave_59: Thanks again Dave:) ...

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UVM

#uvm #uvm_config_db #get_full_name()
Re: SV Assertion

Posted by ben@SystemVerilog.us on Jun 5, 2023
In reply to new_to_uvm: Try something like the following: Keep in mind that task t_aabb() is forked at every @(posedge aa), thus, the 2n posedge of aa will triggered it again. with a guard for a single trigger of the task https://www.edaplayground.com/x/H ...

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SystemVerilog

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