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How to call child class function having only parent class object

Posted by haykp on Apr 1, 2020
SystemVerilog #systemverilog Dear Forum, I have only parent class object, how can I access to its child class function. This is my code: class trans extends uvm_transaction;... endclass class mytrans extends trans; function myPrint (..);... endfunctio ...

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SystemVerilog

#systemverilog
NULL pointer dereference Problem in UVM

Posted by UVM_LOVE on Apr 1, 2020
UVM Start Sequence Method Dear All, I'm trying to understand "NULL pointer dereference" Problem in my UVM First off I do add multiple sequences for running multiple sequence. and then I implement the style of "seq.start(sequencer)" ...

Question
UVM

Start Sequence Method
How make all the $random functions in my testbech to return same value.

Posted by srikanthvvs1 on Apr 1, 2020
SystemVerilog $random My test bench contains multiple $random system task calls in multiple files. There is a constraint that I cannot edit those files. With this given, is there a way to make all those $random system tasks return same value?. Assignment ...

Question
SystemVerilog

$random
Re: How make all the $random functions in my testbech to return same value.

Posted by dave_59 on Apr 1, 2020
In reply to srikanthvvs1: You can override the behavior of a system task by writing your own VPI implementation of it in C. That's relatively easy if you want to override all calls to $random, but if only some, then it gets more complicated to know w ...

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SystemVerilog

$random
doubt in property block (SystemVerilog Assertion)

Posted by aman62 on Apr 1, 2020
SystemVerilog SVA assert property #sequence Here is a code-------- sequence s27a; ©(posedge elk) a##[l:2] b; endsequence sequence s27b; ©(posedge elk) c##[2:3] d; endsequence property p27; ©{posedge elk) s27a and s27b; endproperty a27: assert property(p27 ...

Question
SystemVerilog

SVA assert property #sequence
Re: doubt in property block (SystemVerilog Assertion)

Posted by ben@SystemVerilog.us on Apr 1, 2020
In reply to aman62: Yes becuae each of the sequence have their own clocking events. Ben ...

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SystemVerilog

SVA assert property #sequence
Re: System verilog assertions- not htting criteria

Posted by ben@SystemVerilog.us on Apr 1, 2020
In reply to pkumar16: Quote: Can't we use the followed operator instead of the overlapping operator? #-#, #=#would fail if antecedent or precedent never fired in a run. The followed-by operator is a oroperty that contains a sequence followed by a pro ...

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SystemVerilog
System verilog assertions- not htting criteria

Posted by Naga on Apr 1, 2020
SystemVerilog Hi How we can report an error if a particular assertion doesn't hit even one time throughout simulation? ...

Question
SystemVerilog
Re: Implement transaction logic in driver or sequence class

Posted by ak_verifsj on Apr 1, 2020
In reply to dave_59: Thanks a lot! ...

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UVM

#driver #sequence
Implement transaction logic in driver or sequence class

Posted by ak_verifsj on Apr 1, 2020
UVM #driver #sequence How to generate a transaction- In 25 clks I need to send 15 transaction. These transactions can be send randomly anytime within 25 clks. Should I implement logic in driver class or sequence class and how? ...

Question
UVM

#driver #sequence

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