The Universal Verification Methodology (UVM) is an industry wide collaboration facilitated by Accellera, providing the infrastructure needed to implement a vendor neutral SystemVerilog verification environment. With the UVM, the industry is poised to offer true inter-operability between simulators, testbenches and verification IP for SystemVerilog.
The UVM became an Accellera standard in March of this 2011 and is backwards compatible with the widely adopted Open Verification Methodology.
What You Will Learn
- UVM overview
- A tour of the new UVM library
- Using UVM registers
- OVM to UVM migration
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