Authors:
- Michael Horn - Mentor Graphics
- Bryan Ramirez - Mentor Graphics
- Hans van der Schoot - Mentor Graphics
Abstract:
Parameterized IP continues to expand in usage. Parameterized IP also continues to expand in size which compounds verification complexity. Previous DVCon papers have addressed issues related to using parameters with UVM [1] and employing code, functional and assertion coverage with parameterized IP [2]. They focused on these aspects for conventional simulation. However, with the growing use of emulation for hardware-assisted simulation acceleration, additional considerations emerge. What capabilities does the use of an emulator facilitate, or perhaps impede? How can this be exploited to verify parameterized IP faster and more efficiently?
Introduction:
Semiconductor process technology and FPGA platforms continue to expand the number of transistors and gates that are available for engineers to exploit. The only way to utilize this additional capacity and still meet tight schedules for aggressive time-to-market windows is via the use of Intellectual Property (IP). Consequently, IP reuse is essential to the expansion of the semiconductor industry. Where does all this IP originate? It may come from companies dedicated to developing IP. It may come from FPGA vendors. It may be developed internally within a company.
Regardless of origin, most IP will be used in more than one context. This drives IP creation to yield flexible designs that are parameterized to enable varying configurations to fit different intended use cases. SystemVerilog parameters bring great modeling power, but they also bring great responsibility to design and verification engineers to ensure that parameterized models function correctly. Some of the areas of responsibility have already been investigated in previous DVCon papers [1] [2].
One paper, entitled "Parameters and OVM — Can't They Just Get Along?" [1] discussed various techniques associated with parameters and their interaction with an OVM based environment. Do these techniques continue to work with UVM? What about when emulation is a requirement to accelerate UVM? The following sections will revisit the original paper and address these questions. This involves such aspects as the configuration space, parameterized tests, parameterized virtual interfaces and parameter passing while creating a single unified testbench that can work in both simulation and emulation.
Another paper, entitled "Relieving the Parameterized Coverage Headache" [2] explored the topic of coverage for parameterized IP. The paper content remains largely applicable in the contexts of both UVM and emulation, though some adaptations are necessary. A specific area of emphasis is achieving parameter coverage within a dual domain environment as is required for emulation. Another area of exploration is the employment of SystemVerilog covergroups and cover directives on an emulator to achieve coverage closure faster and more effectively.
The work captured in these earlier papers provide valuable lessons, especially when updated for UVM and coemulation. When an emulator is part of the verification strategy, what unique opportunities does it provide? The emulator brings orders of magnitude improvements in run time performance. This is one of the reasons why an emulator becomes a requirement for a verification effort. The emulator is also a huge resource of parallel execution units. How can that parallelism be exploited? To access the performance and capacity of an emulator, a dual top testbench architecture must be employed. How do two top levels impact parameter usage in the design and a UVM testbench? With the emulator utilizing real hardware, more detailed analysis and compile are required which consequently takes more time than simulation compiles. Targeting real hardware also brings certain limitations on what parts of the SystemVerilog language can be harnessed. How can these considerations be mitigated to allow for full design and parameter exploration? These questions and more will be investigated and answered below.
 View & Download:
Read the entire Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning technical paper.
Source:
DVCon US 2016
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