Authors:
- Bryan Ramirez - Xilinx
- Michael Horn - Mentor Graphics
Abstract:
Verifying a highly parameterized design under test (DUT) that can be used in one of many different configurations requires additional effort over verifying an un-parameterized design or a parameterized DUT used in a single configuration. When using a single configuration, the parameters can be treated as static for the entire process, and the DUT can be verified without worrying about the parameters. However, the verification space grows exponentially if the DUT functionality must be verified over all possible configurations of each parameter. Strategies must be developed to ensure the verification process not only tests all parameterizations but also is as efficient as possible to maximize the number of different parameterizations that can be tested.
This paper will discuss the methods that have proven useful for verifying a highly parameterized DUT within an OVM testbench. This includes enhancing the default OVM functionality to create parameterized OVM tests and, consequently, testbenches that still allow the use of +OVM_TESTNAME. Techniques will be discussed for dealing with parameterized virtual interfaces, efficiently passing parameters down through the testbench hierarchy from the OVM test, and determining when to use parameters versus alternative methods. The paper will discuss optimizations for improving simulation throughput when using parameters, including actual numbers illustrating the efficiency improvements. Finally, the paper will describe options for ensuring that a parameterizable DUT is fully verified.
Introduction:
A highly efficient testbench methodology and architecture that promote reuse are prerequisites to tackling multiple configurations of a parameterized DUT. To that end, the testbench should be built using the Open Verification Methodology (OVM) as testbenches written in OVM yield vast improvements in the construction and reuse of verification code. This is very important when verifying a parameterized DUT that will change functionality based upon the parameter settings.
Writing testbenches using the OVM yields huge improvements in the construction and reuse of verification code. In part this is because OVM provides a library of classes and a methodology for using those classes that promotes consistency in testbench development. However, OVM out-of-the-box is not set up by default to handle situations where both the design under test (DUT) and the testbench share parameters. Sharing parameters is an issue when the design needs to be tested in multiple, parameterized configurations. Several techniques will be described to facilitate parameter sharing and improve simulation throughput when parameters are involved. These techniques include allowing parameterized tests, selecting those tests at run time without having to recompile the code, and handling the required parameterized interfaces. Testbenches that utilize these techniques enable easy design reconfiguration and optimized simulation throughput. We will also describe a set of macros that save time and effort while safeguarding the quality of the design when passing parameters.
 View & Download:
Read the entire Parameters and OVM — Can't They Just Get Along? technical paper.
Source:
DVCon US 2011
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