- Anoop Saha - Mentor Graphics
According to the 2012 functional verification study done by the Wilson Research Group, more than half of total ASIC and FPGA development time is spent in verification, justifiably so. Design bugs, if not isolated and fixed at an early stage, get very tricky and exponentially costlier to resolve later. It is therefore critical to ensure that the verification process is complete; in that it has covered as many scenarios as possible before tape out. This contrasts with the technological advances in the wider semiconductor ecosystem, which are shrinking the time available to bring out a chip in the market. Figure 1 shows the average time spent by engineers in various tasks during the verification process.
For signoff, it is important that all the tests in the verification plan are complete and pass, hitting the right coverage metrics. To speed up this verification process, we need both of the following:
- Maximum reuse to reduce the development time for the tests
- Faster verification to reduce the time and effort required for running the tests, debug, and iterations
In the last few years, the industry has converged on UVM (Universal Verification Methodology) as the standard verification methodology, which enables both horizontal (design to design) and vertical (block to subsystem to full chip) reuse. With the entire semiconductor industry getting behind one universal methodology, verification IP developers must also ship UVM compatible components. The rapid adoption of UVM is a testimony of the significant needs it is able to address.
However, adopting the UVM does not address the other significant verification need: the ability to run, debug, and collect metrics for a large number of tests in a short amount of time. This directly correlates to how fast each test can be run, along with, of course, the technology and the tool used.
During the verification process, engineers typically use a variety of tools. They use logic simulators for block-level verification, which traditionally simulate at 10–1000 clock cycles per second. However, the performance of logic simulators goes down drastically with increased design size, rendering them practically impossible to use for system-level integration testing. Simulation speed is also limited by the number of clock cycles required to run a design; for example, a full video frame in even a moderately sized design will take many, many clock cycles and thus a long time to run in pure software simulation.
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