- Matthew Ballance - Mentor, A Siemens Business
Engineering teams developing complex semiconductors know from experience that functional verification has become the dominant portion of a project’s resources and schedule. Industry studies back this perception up, with many showing that around 70 percent of engineer-hours on a typical chip project are consumed by verification. As nodes shrink and design size grows this trend continues because the verification effort increases much faster than the design effort. Effective design reuse, a key part of all system-on-chip (SoC) projects, has put even more pressure on verification.
Recognizing the need for improved productivity and better quality of results, SoC development teams and EDA vendors have invested much effort in new tools and methodologies for design verification. Three major
trends stand out over the last couple of decades: formal technologies, constrained-random stimulus generation, and hardware acceleration.
Verification flows are no longer homogenous. This is a very good thing. However, there is a lack of test portability across verification platforms and across different levels of design hierarchy.
This white paper discusses portable stimulus, the industry’s solution for verification portability up and down the design hierarchy and across platforms. The Accellera Systems Initiative is currently defining a Portable Stimulus Specification (PSS) standard for verification models that can be used to generate appropriate tests for all levels and platforms automatically. The current draft of the standard (Early Adopter II) includes two alternative input formats for these models. This paper examines the merits and challenges of both formats.
Major Trends in Verification:
Increased use of formal technologies has taken some of the burden off traditional simulation. Assertion-based formal verification is highly effective at the block level, and certain types of formal analysis, such as connectivity checking, work well on a complete chip design.
Constrained-random stimulus generation has become the primary simulation-based method, due in part to the popularity of the Universal Verification Methodology (UVM) standard from the Accellera Systems Initiative. This approach enables an automated stimulus-generation process that creates many more tests than manual methods. The UVM clearly defines the components that make up a verification testbench, fostering internal verification reuse while enabling a commercial business in verification IP (VIP).
Increased reliance on verification hardware is the third recent trend. The UVM works with hardware acceleration as well as software simulation. Many SoC teams move on to in-circuit emulation (ICE) or FPGA-based prototypes to run tests more quickly and to make use of real-world scenarios. However, there is no testbench involved in either ICE or prototypes, so the UVM does not apply. Thus, portability across verification platforms is missing in a flow based purely on constrained-random stimulus.
The UVM also fails at providing portability across different levels of design hierarchy. Figure 1 shows a generic UVM-style testbench for Block A. Stimulus is driven to the inputs on all interfaces by “active” testbench components, while “passive” components monitor and check results and coverage. Some sort of top-level testbench control is needed to coordinate stimulus and check results against predicted values. Figure 1 shows a second block, B, with a very similar testbench.
View & Download:
Read the entire Choosing a Format for the Portable Stimulus Specification technical paper.