Authors:
- Anwesha Choudhury - Mentor Graphics
- Ashish Hari - Mentor Graphics
Abstract:
Increasing usage of multi-clocking architecture to meet high performance and low power requirements of the modern SOCs makes clock domain crossing (CDC) verification a critical step in design verification cycle. CDC verification is not only necessary on RTL; it is also a necessity on gate-level designs due to the possibility of the introduction of CDC errors during the synthesis phase that can lead to silicon failure. However, CDC closure on gate-level designs continues to be one of the most difficult tasks during the verification cycle because of very high setup effort, stretched performance and high noise in the results. In this paper, we review the root cause of these challenges and introduce an automated approach to overcome these difficulties. The proposed methodology is based on learnings from complete verification process and utilization of knowledge gained from prior verification steps to automate and accelerate gate-level CDC verification clo-sure. The proposed methodology enhances gate-level CDC verification experience for the user by automating the setup, accelerating performance, eliminating noise, and easing debug.
Introduction:
CDC verification ensures that signals pass across asynchronous clock domains without being missed or causing metastability. Traditionally, CDC verification is done on a register-transfer level (RTL) representation of the design. However, during the synthesis stage, when the design is transformed from RTL to gate level, various new issues can be introduced that may eventually lead to chip failures. So, even after CDC verification closure at the RTL, it is important to perform CDC verification on a gate-level design to detect and address new issues.
Changes introduced in the netlist during synthesis, such as timing optimization of synchronization logic and insertion of design-for-test (DFT) and low-power circuitry may cause incorrect behavior in CDC synchronizers, introduce new CDC paths or break valid CDC paths. For example, new clock domain crossings can be introduced due to insertion of low-power logic as shown in Figure 1. Similarly, due to scan logic insertion, a clock tree can be impacted if the correct mode design constraints are not specified, as shown in Figure 2.
Additionally, faulty implementation of combinational logic by synthesis tools may result in glitches on control and data paths. As shown in as shown in Figure 3, a valid mux-based synchronizer is converted to a combinational logic which is logically correct, but can propagate a glitch from asynchronous transmit domain causing chip failure.
 View & Download:
Read the entire Accelerating CDC Verification Closure on Gate-Level Designs technical paper.
Source:
DVCon 2017
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