- Awashesh Kumar - Mentor, A Siemens Business
- Madhur Bhargava - Mentor, A Siemens Business
With the advancement in the technology, the size and complexity of SoC is ever increasing. At the same time the power constraints on those SoC are getting more stringent. The low power designs are getting more and more complex with large number of power domain, supplies and power states. This makes the job of low power SoC verification overwhelmingly complex, tedious and sophisticated. It is the need of the hour to develop a reliable verification methodology which is easy to build, easy to understand and easy to modify. UPF 3.0 – The IEEE standard to specify the low power intent, has introduced a concept of low-power information model which can be useful to address the complex verification challenges. This paper introduces the key concepts of UPF 3.0 information model which are useful from low-power verification point of view. The paper proposes a low-power coverage methodology based on the UPF 3.0 information model HDL package. The paper also includes relevant case studies and examples using the proposed methodology to solve low-power verification problems. It also discusses the benefits of this approach and its advantages over conventional low-power verification approaches. There are still some areas like analog and mixed signal low power verification where the proposed coverage methodology cannot be used.
With the advancement in the technology, low-power designs and its verification is becoming more complex. Today's chips have multiple power domains each having multiple operating power modes and dynamically changing voltage levels. The power architecture is controlled with help of a power management unit which issues proper control sequences to different elements of the power architecture. It is important to ensure that all and proper test vectors are generated by this unit to verify all power elements and it is even more important to verify the complex interactions between these elements at a higher abstraction level. A plan to closure approach for low-power verification requires coverage of power objects (all possible states and transitions). However power-aware coverage closure is hard and complex in nature.
It is important to note that there is no standardized methodology for low-power coverage, as UPF 2.1 doesn't provide anything to address this. With the help of current UPF standards, verification engineers have taken the ad-hoc approach to achieve coverage of some constructs and their interactions with each other e.g. power states etc. One such technique is cross-coverage of power states. However it is prone to state explosions and it involves low level intricate efforts to write the covergroups and coverbins for the cross-coverage. Verification engineer needs to be well aware of the UPF to figure out the supplies and signals to track. Moreover this whole process is tedious and dependent on verification tools and EDA vendors. The whole process is error prone and highly time consuming. So a faster and direct approach to address low power coverage is a need of the hour.
To keep pace with that, IEEE 1801 standard is expanding its gamut of constructs and commands to include more scenarios of low-power verification and implementation. In this paper, we will discuss and propose a methodology by which effective coverage of low-power verification can be achieved using UPF 3.0. With the help of relevant examples and case studies we will also demonstrate that with the help of this methodology, the coverage closure can be achieved in much efficient way thereby significantly saving the verification effort and time.
A. Power Intent Specification and Basic Concepts of UPF
IEEE Std 1801™-2015 Unified Power Format (UPF) allows designers to specify the power intent of the design. It is based on Tcl and provides concepts and commands which are necessary to describe the power management requirements for IPs or complete SoCs. A power intent specification in UPF is used throughout the design flow; however it may be refined at various steps in the design cycle. Some of the important concepts and terminology used in power intent specification are the following:
- Power domain: A collection of HDL module instances and/or library cells that are treated as a group for power management purposes. The instances of a power domain typically, but do not always, share a primary supply set and typically are all in the same power state at a given time. This group of instances is referred to as the extent of a power domain.
- Power state: The state of a supply net, supply port, supply set, or power domain. It is an abstract representation of the voltage and current characteristics of a power supply, and also an abstract representation of the operating mode of the elements of a power domain or of a module instance (e.g., on, off, sleep).
- Isolation Cell: An instance that passes logic values during normal mode operation and clamps its output to some specified logic value when a control signal is asserted. It is required when the driving logic supply is switched off while the receiving logic supply is still on.
- Level Shifter: An instance that translates signal values from an input voltage swing to a different output voltage swing.
- Retention: Enhanced functionality associated with selected sequential elements or a memory such that memory values can be preserved during the power-down state of the primary supplies.
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Read the entire Random Directed Low-Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure technical paper.