As SoC and ASIC designs continue growing in both size and complexity and FPGA devices now becoming SoCs themselves, design and verification teams are constantly searching for ways to increase their verification productivity and design quality to keep up with this growing challenge. There have been several methodologies introduced in the past that are aimed at addressing these challenges. Accellera's Universal Verification Methodology (UVM), with its library created in SystemVerilog, is the first methodology that incorporates lessons learned from those previous methodologies and is supported and endorsed by all three major vendors in addition to a growing Eco-System of providers.
There is a great deal of buzz around UVM today. Engineers and managers want to understand better how it will benefit them, what effort will it take to adopt, what is available to help, how they fit it into their current environment and do they have the right people to maximize its benefits.
This seminar will deliver a comprehensive overview of how UVM can be used for maximum verification throughput and the tools available around it to both ease adoption and improve productivity. During this seminar you will learn:
- Keys and techniques for effective Verification Planning and Management for UVM.
- A staged approach for UVM adoption using UVM Express.
- Tools and techniques to track Design Requirements through verification.
- Tools and techniques to manage verification regression runs, track verification and simulation with a testplan, automatically analyze results, instantly understand status of projects, and analyze trends during verification.
- Best practices and tools to create your UVM testbench and capabilities of UVM Verification IP.
- Best practices and tools to effectively debug your UVM testbench alongside your design.
- How to automate, track and accelerate coverage closure.
- Complementing UVM with easy to use static tools for more comprehensive verification.
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