Intent:
Encapsulate small, useful functionality in a portable, easy-to-use object.
Motivation:
In many cases a full verification component such as a UVM agent has more code and functionality than is required to perform a task. A small portable object derived from uvm_object or a standalone SystemVerilog package is sufficient in many cases.
Applicability:
The utility pattern is useful for encapsulating small, focused functionality.
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