Intent:
The SW-HW Pipe Pattern is an implementation pattern that provides a buffered one-way communication channel between separated HVL and HDL module hierarchies in a dual-domain partitioned testbench. Writing to and reading from the pipe can be done at any rate. Writes block if the pipe is full. Data written to an empty pipe is available for reading on the next clock cycle. Reading from an empty pipe has a well-defined behavior.
Motivation:
Implementing an efficient driver in a dual-domain testbench with partitioned HVL and HDL module hierarchies targeted for the simulator and emulator can be problematic as the nature of a driver in a reactive testbench dictates that the UVM driver is not always able to provide data in advance, or provide any data at all. At the same time, the testbench should be able to react to events in the DUT with little delay. In order to facilitate optimization of the HVL-HDL (or inbound) cross-domain communication channel, it should be implemented using one-way, non-blocking function calls. However, the generally unpredictable rates of writing to, and reading from, the channel requires a return path for the implicit state (i.e. the buffer fill level) of the channel. A return HDL-HVL (or outbound) call must be decoupled from its corresponding forward HVL-HDL call to enable optimization of the latter in environments that support it. The frequency of return path calls is reduced in proportion to the size of the buffer.
Applicability:
The SW-HW Pipe Pattern is applicable in any situation that requires reactive one-way transfer of data between separated HVL and HDL domains in a common dual-domain testbench context. The pattern is pertinent especially if the transfer is part of a reactive loop of the testbench.
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