The Environment Layering Pattern is used to provide consistent configuration and structure for vertical reuse of environments.
Block level environments are used to test specific scenarios and close coverage. Subsystem and chip level environments are used to test integration and traffic patterns. Reusing block environments within subsystem environment and subsystem environments within chip environments leverages existing bug identification, analysis and coverage in upper level simulations. The Environment Layering Pattern can be used to provide consistent component encapsulation.
The Environment Layering Pattern can be used when performing vertical reuse of components within other components.
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