Intent:
To effectively verify connectivity between various modules such as Address and Data bus.
Motivation:
We typically keen on looking at toggle coverage of address and data bus connection at SoC level, as the key effort in Verification at SoC level is focused on integration. We would also be interested in collecting one-hot or one-cold encoding coverage.
Applicability:
This pattern will be applicable for anyone focused on integration verification. These are very commonly patterns used in stimulus and verification of RAM address and bus connectivity. This pattern can be used as Stimulus Pattern and an Analysis Pattern.
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