WILSONVILLE, Ore., April 10, 2014 – Mentor Graphics Corp. (Nasdaq: MENT), today announced the Mentor® Enterprise Verification Platform (EVP), which combines Questa® advanced verification solutions, Veloce® OS3 global emulation resourcing technology, and Visualizer™, a powerful debug environment, into a globally accessible, high-performance datacenter resource. The Mentor EVP features global resource management that supports project teams around the world, maximizing both user productivity and total verification return on investment. The Mentor EVP delivers performance and productivity improvements ranging from 400X to 10,000X.
“Mentor’s verification vision is to deliver an environment where the verification process is completely abstracted from the underlying verification engines from first design thoughts, through silicon, to final product,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “With EVP, Mentor has eliminated the barriers to hardware acceleration and ushered in a new era of enterprise-level verification that combines the functionality and observability of simulation-based verification with the speed of emulation.”
Veloce OS3 and Mentor VIP Transform Emulation into a Global, High-Performance Datacenter Resource
To leverage the investment in emulation and allow it to serve as a true enterprise verification resource, emulation must undergo a transformation from project-bound engineering lab instrument to datacenter-hosted global resource. This transformation begins by eliminating the In-Circuit Emulation (ICE) tangle of cables, speed adaptors and physical devices, replacing them with virtual devices. The Veloce OS3 VirtuaLAB peripherals are reconfigured instantly to support multiple projects and rapidly shifting priorities. This is possible because VirtuaLAB is hosted on standard datacenter computers, not proprietary hardware targets.
The OS3 Enterprise Server efficiently manages the global emulation resources, consolidating them to commercial queue managers as a single, high-capacity entity. The Enterprise Server determines the most efficient location to run each job and immediately serves high-priority jobs by temporarily suspending jobs of lower priority.
Veloce OS3 also delivers advanced verification features to the emulator including PSL/SystemVerilog assertions, functional coverage, and UPF for low power. This enables a high-performance coverage closure flow and pre-silicon performance analysis of critical SoC subsystems running application software. To maximize testbench reuse, the Mentor Verification IP, built using standard UVM/RTL, is designed for both simulation and acceleration modes. These capabilities are in place for a smooth transition from simulation to emulation, allowing for a 1000X performance boost over simulation alone with no loss of functionality.