Join the Verification Academy technology experts each month for this online series. This series will feature sessions discussing the very latest on coverage closure, stimulus generation, fast and efficient VIP, debug techniques that will help you answer the age old question "am I done yet", details for designing an efficient UVM Testbench, new approaches for Software Driven Verification and more!
Web seminar topics include:
With the complexity and interoperability needs of today's systems the use of standard interfaces such as PCIe and MIPI is a must. Verification of IP to implement these interfaces for re-use within a wide variety of systems can be time consuming and hard to get right. Users of IP are often faced with issues of integration and getting caught in the complex details of the IP implementation when their real goal is to verify design specific and system functionality. Verification IP is available to solve these issues, but too often comes with a high integration effort and a steep learning curve of its own that users must overcome before they can become truly productive.
This webinar will cover the use of UVM based verification IP for protocols such as PCI Express and MIPI CSI and DSI
Management of complex SoC development projects to the point of successful coverage closure has become a very challenging job. Design and verification engineers spend enormous amounts of time reviewing coverage holes. This presentation discusses a new school formal verification method which automates the job of focusing coverage closure efforts on the items which actually need to be hit and the results achieved on a large SoC design in the entertainment and signal processing domain.
This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.
One of the primary goals of SoC-level verification is to ensure that all top-level connections have been made correctly. However, this is no easy task. Today's SoC designs contain large numbers of design IP blocks, interconnected through multiple on-chip bus fabrics and point-to-point connections, which can result in interconnect signals that number in the thousands. This session discusses the use of a new school formal verification method which can be easily applied to solve the problem of connectivity checking with detailed case studies of how this formal app was used to automatically verify connectivity and accelerate the debug process.
Techniques for generating verification stimulus have been around as long there have been designs to verify. As the designs being verified have become more complex, stimulus generation techniques have evolved to address the emerging requirements. From directed tests to random test generation to graph-based intelligent testbench automation, development of these stimulus generation techniques has evolved from specific verification challenges. The development of a new stimulus generation technique rarely results in the obsolescence of previously-created stimulus generation techniques. Picking the right stimulus generation techniques to use is crucial to efficiently achieving quality functional verification results. This session will explore the three dominant stimulus generation techniques used today for functional verification to identify; the characteristics of stimulus generated by each technique, where each technique best applies on its own and how these new school techniques can be combined to achieve even greater verification value.
The debug activity takes a significant proportion of any design or verification engineer's time and there is much we in the Design Automation industry can do to improve individual and team productivity in this area. It starts with putting ourselves in the users' shoes and designing a complete solution, not just 80% of a solution. Gordon Allan takes a critical look at the past, present and future challenges for debug, exploring real world situations drawn from years of experience in SoC design and verification, and describing leading-edge techniques and compelling solutions.
Getting the very best from your verification resources requires a regression system that understands the verification process and is tightly integrated with Workload Management and Distributed Resource Management software. Both requirements depend on visibility into available software and hardware resources, and by combining their strengths, users can massively improve productivity by reducing unnecessary verification cycles.
This session will show how adding control and visibility to these systems, and then better integrating them, will help your organization get the very best from every verification dollar. It will also highlight how separating control from the configuration data in a regression system improves maintenance and user productivity. Major features can be coded into the system itself instead of added as a series of scripts with multiple calling levels, which often lead to a debug nightmare.
IEEE 1801 UPF enables specification of power intent early in the design flow, to drive both verification and implementation processes. But power management decisions must be made incrementally throughout the flow, often by different people at each stage. Power intent specifications need to be structured in a manner that reflects these stages, to organize the information effectively, to ensure clear communication among IP providers, designers, and implementers, and to maximize reuse of power intent. This session highlights a "new school" low power methodology termed "successive refinement" that uses the strength of UPF in just such a structured approach. It will explain what kinds of power intent information should be captured at each stage, which features of UPF are involved in doing so, and how this structured approach benefits both IP providers and IP users.
View or download all of the Verification Academy Technology web seminars.