Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • Low Power Verification - 4/29
      • Fault Campaign for Mixed-Signal - 5/4
      • User2User - 5/26
      • Webinar Calendar
    • On-Demand Webinars

      • CDC+RDC Analysis
      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • Achieving High Defect Coverage
      • Visualizer Features
      • All On-Demand Webinars
    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings
    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences
    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us
    • Training

      • Questa Basic
      • Questa Advanced
      • Mastering Questa
  • Home
  • News
  • Mentor’s next-generation Questa inFact to fully support Accellera’s Portable Test and Stimulus Standard 1.0

Mentor’s next-generation Questa inFact to fully support Accellera’s Portable Test and Stimulus Standard 1.0

Mentor, a Siemens business, which pioneered portable stimulus technology in 2004, announced it will fully support the new Accellera Portable Test and Stimulus Standard 1.0 in the upcoming release of its Questa® inFact™ tool. The Accellera standard, which is based on Questa inFact technology that Mentor donated to Accellera in 2014, will rapidly drive portable stimulus into broader, mainstream use and help IC engineers more efficiently collaborate and deliver innovation to markets such as artificial intelligence, 5G wireless communication and autonomous driving.

At its core, the new Accellera portable stimulus standard (PSS) enables engineers to re-use a single set of portable stimulus specifications across multiple verification engines to achieve different objectives at various stages of the development process. Mentor’s Questa inFact tool is the industry’s most comprehensive solution, supporting design, verification, validation and test. It leverages machine learning and data mining techniques that have yielded up to a 40X increase in productivity across multiple phases of customer IC development. The Questa InFact tool leverages portable stimulus technology, enabling designers to complete advanced performance and power analysis at the IC level, verification engineers to achieve higher levels of coverage in less time, validation engineers to fully integrate hardware and software, and test engineers to analyze and optimize their regression test environments.

“When Mentor donated the Questa inFact tool’s language and initiated the original Accellera Portable Test and Stimulus Working Group in 2014, we did so to drive portable stimulus toward mainstream use and help more design teams realize the step-function gains in verification productivity afforded by our Questa inFact tool,” said Mark Olen, product marketing group manager for the Mentor IC Verification Solutions Division. “As we’ve collaborated with Accellera’s PSS working group to drive the specification to this standard over the last four years, we’ve also been diligently refining Questa inFact to comply with the portable specification as it has evolved. We have additionally added the latest machine learning and data mining technologies to expand the Questa inFact tool’s use for the design, validation and regression test phases of the IC development process.”

Customers use the Questa inFact tool to generate UVM SystemVerilog test scenarios to achieve functional coverage at the IP block level with the Questa simulator, and then re-use the test scenarios to generate C/C++ tests for traffic generation at IC level verification with the Veloce® emulator. Customers also use the Questa inFact tool to generate assembly code at the system level for instruction-set verification. In addition, the tool can generate C/C++ scenarios for architectural exploration with the Vista™ virtual prototyping system. Lastly, customers use the Questa inFact tool in concert with Mentor’s Catapult® High-Level Synthesis toolset by generating C/C++ scenarios before, and RTL tests after, behavioral synthesis.

Mentor has applied classification machine learning to its graph-based Questa inFact technology to enable the actual targeting of scenarios not yet verified. This enables much faster achievement of coverage goals at the IP block level, and increased usefulness of bare metal testing at the IC level. Mentor’s Questa inFact tool learns from each subsequent scenario during simulation or emulation -- the longer it runs, the smarter it gets.

Mentor has also applied data mining technology to extend the application of portable stimulus beyond verification. The Questa inFact tool can collect and correlate transaction-level activity to characterize IC design performance parameters including fabric routing efficiency and bandwidth, system-level latency, cache coherency, arbitration efficiency, out-of-order execution, and even opcode performance. It can also analyze and optimize regression test environments, eliminating costly and redundant simulation and emulation cycles.

“We have been using early versions of this standard in Mentor’s Questa inFact tool for many years to help customers leverage PSS to achieve their design goals,” said Srini Venkataramanan, chief technology officer for Contemporary Verification Consultants, Ltd. (CVC). “With the new Accellera standard in place, we believe adoption will accelerate and we will be able to help customers achieve even greater success."

Mentor initiated the formation of the Portable Test and Stimulus Working Group in June 2014, and has continued to collaborate with industry participants in the Accellera Portable Stimulus Working Group to help deliver this first version of the standard.

To learn more about Mentor’s Questa inFact tool, visit Mentor at booth #2621 or the Verification Academy at booth #1622 during this week’s Design Automation Conference in San Francisco’s Moscone Center June 25th - 28th.

For More Information

Jack Taylor
jack_taylor@mentor.com
Mentor Graphics
512-560-7143

Related Products

Questa® inFact

Questa inFact targets as much functionality as traditional constrained random testing, but achieves coverage goals 10X to 100X faster.
Learn More

About Mentor Graphics

Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.  Web site: http://www.mentor.com.

Mentor Graphics, Mentor, Questa, Veloce and Catapult are registered trademarks and inFact is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owner.

← Back to News

Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 547 3000

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy