Please join Subject Matter Expert, Jim Lewis from SynthWorks as he demonstrates the latest enhancements to VHDL-2008. Mr. Lewis recorded seven sessions for the Verification Academy covering VHDL-2008 topics including:
- VHDL-2008 Overview
This session is a brief overview of all the VHDL-2008 improvements
- Testbench Enhancements
Through extended and new capability, VHDL-2008 enables the creation of advanced verification environments. This session examines these changes and the value they deliver.
- RTL Enhancements
VHDL-2008 enhancements simplify RTL coding. Among these changes are simplified sensitivity lists, simplified conditionals (if statements), and simplified case statements. This session examines these changes and the value they deliver.
- Operator Enhancements
This session will discuss the value of the many new enhancements to the VHDL-2008 operators including Unary reduction, Array operations and mods for physical time.
- Package Type Enhancements
VHDL-2008 includes numerous tune ups to the packages and how the packages are integrated into the language. The session explores the new packages and modifications to the packages as well as the value these updates deliver.
- Fixed Point Package
The new package, fixed_generic_pkg, defines fixed point math types and operations. This session will explain the details of the new package.
- Floating Point Package
The new package, float_generic_pkg, defines floating point math types and operations. This session will explain the details of the new package.
View the new VHDL-2008 Why It Matters Course.