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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
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    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
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      • Power Aware CDC Verification
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      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
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    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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      • Introduction
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  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Mentor Graphics Veloce Emulation Platform Helps Barefoot Networks Verify the World’s First Fully Programmable Switch

Mentor Graphics Veloce Emulation Platform Helps Barefoot Networks Verify the World’s First Fully Programmable Switch

WILSONVILLE, Ore., July 19, 2016 – Mentor Graphics Corporation (NASDAQ: MENT) today announced that the Veloce® emulation platform was successfully used by Barefoot Networks, a pioneer in building user-programmable and high-performance network switches, to verify its 6.5Tbps TofinoTM switch. Barefoot chose the Veloce emulation platform for its high capacity, superior virtualization technology, remote access option and proven track record in networking design verification.

Barefoot Networks benchmarked the different emulators available, and after a careful and lengthy evaluation, decided the Veloce platform was the only emulator able to handle the large and complex Barefoot Networks design.

“The Veloce emulation platform gave us the capacity we needed to verify our programmable, networking-specific and interconnect-dominated design,” said Dan Lenoski, VP of Engineering, Barefoot Networks. “Beyond the fundamental strengths of the Veloce emulation platform, we were also able to take advantage of their proven hardware+software co-emulation, which is critical for verifying a programmable networking device.”

In the networking space, Ethernet designs are large and particularly intricate, and can tax emulation compile and run times. The Barefoot’s Tofino switch design consists of complex interconnect, which typically creates a challenge for most emulation platforms to route.  The Veloce emulation platform uses patented virtual wire technology and the proprietary Crystal2 chip, and had no issue handling the complexity of this interconnect-dominated design.

In addition, the Veloce VirtuaLAB Ethernet used by Barefoot was critical for testing the core functionality of the design. VirtuaLAB includes an Ethernet Packet Generator and Monitor (EPGM) that generates, transmits and monitors Ethernet packets with the Design under Test (DUT); Ethernet testers are modeled in software running under Linux on a workstation connected to the emulator.

 “The Veloce emulation platform continues to dominate in the networking market,” said Eric Selosse, vice president and general manager of the Mentor Emulation Division. “We worked with Barefoot on access and implementation so they could focus immediately and exclusively on the verification task.”

About the Veloce Emulation platform

The Veloce emulation platform uses innovative software, running on powerful, qualified hardware and an extensible operating system, to target design risks faster than hardware-centric strategies. Now considered among the most versatile and powerful of verification tools, emulation greatly expands the ability of project teams to do hardware debugging, hardware/software co-verification or integration, system-level prototyping, low-power verification and power estimation and performance characterization.

The Veloce emulation platform is a core technology in the Mentor® Enterprise Verification Platform™ (EVP) – a platform that boosts productivity in ASIC and SoC functional verification by combining advanced verification technologies in a comprehensive platform. The Mentor EVP combines Questa® advanced verification solutions, the Veloce emulation platform, and the Visualizer™ debug environment into a globally accessible, high-performance, datacenter resource. The Mentor EVP features global resource management that supports project teams around the world, maximizing both user productivity and total verification return on investment.

Mentor Graphics, Mentor and Veloce are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

For more information

Suzanne Graham
suzanne_graham@mentor.com
Mentor Graphics
503.685.7789

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Veloce2 Emulator

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Veloce VirtuaLAB

Veloce VirtuaLAB emulation solutions provide software-based, full applications for the verification of complex SoCs without the need for external hardware.
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About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design and manufacturing solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year of approximately $1.18 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Website: https://www.mentor.com/.

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