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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
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    • Methodologies

      • UVM - Universal Verification Methodology
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    • Techniques & Tools

      • Verification IP
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      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • CDC+RDC Analysis - 4/20
      • Low Power Verification - 4/29
      • User2User - 5/26
      • Webinar Calendar
    • On-Demand Webinars

      • Basic Abstraction Techniques
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      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • Achieving High Defect Coverage
      • Visualizer Features
      • Questa Static and Formal Apps
      • All On-Demand Webinars
    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
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    • Conferences

      • DVCon 2021
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      • DAC 2019
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    • Mentor Learning Center

      • SystemVerilog Fundamentals
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      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification Horizons Blog
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    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
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    • Training

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  • Verification Horizons
  • Mentor Graphics Veloce 2 Emulation Platform Boosts Verification Productivity for STMicroelectronics

Mentor Graphics Veloce 2 Emulation Platform Boosts Verification Productivity for STMicroelectronics

WILSONVILLE, Ore., May 29, 2014  – Mentor Graphics Corp. (Nasdaq: MENT), a leader in advanced system verification solutions, announced today that STMicroelectronics (ST), a global semiconductor leader serving customers across the spectrum of electronics applications, has adopted the Veloce® 2 emulation platform to boost productivity in the verification of System-On-Chip (SoC) and Intellectual Property (IP)-based designs.

The Veloce 2 platform delivers a flexible emulation environment capable of handling small and large designs where the platform can be easily and quickly reconfigured to suit the needs of an IP design user or a SoC user. With the Veloce enterprise server features, this is achieved simply and automatically, allowing users to maximize a valuable resource. The Veloce 2 platform allows any user to access one or more of its advanced verification boards, thereby using all hardware resources available across many individuals or groups.

“Since 2009, STMicroelectronics has used Mentor Veloce for the emulation of complete system-level HW/SW verification and validation of many complex SoC platforms. This capability enables us to routinely bring up full-system boot within hours of receiving 28nm SoC silicon. The Veloce 2 platform is now used across our multiple SoC platforms, including our latest HEVC-based consumer SoCs, and the consumer ASICs that we develop with our customers on ST's 28nm fully depleted Silicon-on-Insulator (FD-SOI) process technology,” said Philippe Magarshack, Executive Vice President of Design Enablement and Services at STMicroelectronics. “By pioneering the usage of Veloce 2 as a shareable, global emulation resource, we have significantly improved the productivity and time-to-market of our multiple SoC design teams while maximizing hardware utilization.”

Delivering multiple verification methodologies using the Veloce 2 platform satisfies the needs of different design teams who have unique approaches to system verification and validation. These approaches span acceleration methodologies, using both SystemC and SystemVerilog/UVM testbench environments, traditional In-Circuit emulation (ICE), and virtual emulation techniques based on the Veloce VirtuaLAB platform capabilities.

“As a long-time user, STMicroelectronics pushes the boundaries of hardware emulation to verify their complex IP and systems,” said Eric Selosse, Vice President and General Manager, Mentor Emulation Division. “By meeting ST’s needs with the Veloce 2 emulation platform, we help them successfully achieve a high-level of pre-silicon verification. ST takes their emulation use to another level of effectiveness by allocating hardware and software resources automatically, across multiple geographies, where they can treat the emulator as a shareable, always-on, networked resource for hardware and software teams.”

About the Veloce Emulation Platform

The Veloce 2 emulation platform is the latest-generation hardware emulator from Mentor that reduces project schedules and costs by delivering high-performance simulation accelerations, virtualized emulation, and traditional in-circuit emulation of complex SoC designs. The Veloce 2 platform achieves these benefits through a unique emulation-on-chip architecture and best-in-class software and hardware technologies, delivering fast compiles, full debug visibility, power aware and analysis tools, and advanced memory modeling. Additionally, leading-edge protocol solutions provide off-the-shelf portfolios of easy-to-use verification IPs (VIPs), ICE applications (iSolve™), and VirtuaLAB components that are an essential part of verifying both IP and SoC-based designs, delivering high levels of productivity and ROI to the end user.

Mentor Graphics and Veloce are registered trademarks and iSolve is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners

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