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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
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      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
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      • Start Here - Patterns Library Overview
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
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      • Register Abstraction Layer
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      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
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      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • Low Power Verification - 4/29
      • Fault Campaign for Mixed-Signal - 5/4
      • User2User - 5/26
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

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      • Verification Horizons - November 2020
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  • Verification Horizons
  • Mentor Graphics Proposes New Accellera Standards Committee for Graph-Based Test Specification Standard

Mentor Graphics Proposes New Accellera Standards Committee for Graph-Based Test Specification Standard

WILSONVILLE, Ore., March 4, 2014 - Mentor Graphics Corp. (NASDAQ: MENT), today announced it has proposed that a new Accellera standards committee be formed to investigate the standardization of a graph-based test specification standard. To underscore this endeavor, Mentor will make a technical donation of its existing graph-based test specification format to jump-start the standardization effort.

“The Mentor graph-based specification technology brings compelling new value to the verification domain with its capabilities for quickly and exhaustively covering the device state space,” said Peter Jensen, owner and managing director, SyoSil. “This lets us use a unified graph-based description for traditional coverage-driven verification using UVM at the block level, as well as intelligent software-driven verification using embedded C test programs at the system level.” 

“Having access to the most advanced functional verification methodologies is essential to maximize electronic design and verification efficiency, and we have seen customers realize a ten-fold gain in productivity through the adoption of graph-based test technology,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “Based on customer feedback, we’re moving forward to recommend and facilitate a standards effort that brings significant benefits to a large number of users, and opens the door to technology innovation.”

Benefits of a Graph-Based Test Specification

The benefits of graph-based test specification are threefold. First, it reduces the time spent writing and debugging tests by 50% or more.  Verification engineers can use the graph-based specification format to describe the exact same test universes currently described in their existing SystemVerilog UVM constraint-based tests, in less than half the lines of code, without any change to the test intent. This also means a reduction in the number of test bugs, enabling verification engineers to focus on debugging their designs, not their tests.

Second, the graph-based test specification format naturally supports multiple design languages and multiple verification environments enabling re-use across both design context and verification engines. The same graph-based test specification can be used in a SystemVerilog UVM testbench environment for block-level simulation, as well as in an embedded C test program for system-level emulation. It can also be used to generate instructions for microprocessor instruction set verification, and it can even be used on target hardware including FPGA prototyping and post-silicon validation.

Third, the abstract nature of a graph-based test specification lets tool implementations execute the test specification in different ways according to verification requirements. For example, a tool with a graph-based test specification can be instructed to execute the test specification in a systematic way to quickly achieve functional coverage during the early stages of a verification project. At a later time, the tool can be instructed to execute the test specification in a completely random manner to produce soak tests on a simulation farm for regression testing.

Mentor’s Donation to the Graph-Based Test Specification Standards Effort

The graph-based specification format is not new to verification. It is based on the standard Backus-Naur Form (BNF), pioneered by IBM, and has been used by many companies to automate compiler testing. Its natural atomic architecture closely mimics the structure of a typical design specification, making requirements mapping easy and straightforward. The graph-based specification format being donated by Mentor Graphics has been augmented to support VLSI design verification across all standard environments and languages including Verilog, VHDL, SystemVerilog, e, SystemC, C/C++, assembly code.

Mentor Graphics is a registered trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

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