Verification Academy

Search form

My Account Menu

  • Register
  • Log In
  • Topics
  • Courses
  • Forums
  • Patterns Library
  • Cookbooks
  • Events
  • More
  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages
    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage
    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • UVM Forum
    • SystemVerilog Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • SystemVerilog Forum
    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum
    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns
    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • Low Power Verification - 4/29
      • Fault Campaign for Mixed-Signal - 5/4
      • User2User - 5/26
      • Webinar Calendar
    • On-Demand Webinars

      • CDC+RDC Analysis
      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • Achieving High Defect Coverage
      • Visualizer Features
      • All On-Demand Webinars
    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings
    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences
    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Academy Newsletter
      • Technical Resources
    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
      • Verification Horizons - July 2020
      • Issue Archive
    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us
    • Training

      • Questa Basic
      • Questa Advanced
      • Mastering Questa
  • Verification Horizons
  • Mentor Graphics Delivers Emulation Solutions for the Verification of PCI Express Gen3 Products

Mentor Graphics Delivers Emulation Solutions for the Verification of PCI Express Gen3 Products

WILSONVILLE, Ore., November 1, 2012—Mentor Graphics Corp. (NASDAQ: MENT), a leader in advanced system verification solutions, today announced hardware and software solutions to accelerate the verification of PCI Express Generation 3 products. These new solutions, when connected to a Veloce® emulator, enable designers to test the new generation PCI Express devices on their System-on-Chip (SoC) designs, and to develop and test their software drivers and firmware prior to silicon being available.

The iSolve™ PCI Express Gen3, which has a ‘plug-and-play’ hardware interface to the Veloce family of hardware emulators, provides a cost-effective and efficient solution to verify PCI Express Gen3 devices on a SoC design. The Gen3 product is also fully compatible with older Gen1 and Gen2 speed devices. This new solution adds to the existing iSolve family of products for the accelerated verification of applications such as multimedia, networking, embedded systems, wireless, and storage devices.

Complementing the iSolve product is a new Veloce PCI Express Gen3 Transactor, which delivers an accelerated simulation environment for the verification of PCI Express Gen3-compliant devices. It generates the appropriate stimuli for the Design-Under-Test (DUT), passing packets, or transactions, of protocol data for tests. The transactor also provides a high-level Application Programming Interface (API) to allow use with multiple test-bench environments, such as SystemVerilog/UVM and SystemC, and provides example test environments that can exercise the emulated PCI Express Gen3 device.

Increased bandwidth and performance requirements of modern PCs and servers, especially those involving high-speed graphics, have made PCI Express an industry standard. As a result, PCI Express motherboards and associated peripherals, such as multi-gigabit Ethernet cards and RAID controllers, have become widespread and popular. With such a prevalence of new products for PCI Express applications, the need for a solution that allows the verification of these products and applications has become more critical and is in high demand. The latest generation of PCI Express, Gen3, increases this need further.

“The growth in PCI Express products has been increasing rapidly, and is especially important to those in the server, gaming and entertainment sectors where increased data throughput and high-speed graphics are mandatory for the operation of applications,” said Eric Selosse, vice president and general manager, Mentor Emulation Division. “The challenges faced by the creators of such systems are complex, and require high-performance verification solutions to detect flaws early in the development cycle and to reduce risks. To solve these challenges, we created both hardware and software solutions for the verification of PCI Express Gen3 products. These solutions provide more flexibility and ease-of-use, and the configurable test models that our customers require for pre-and post-silicon testing.”

The new PCI Express Gen3 products deliver use modes with traditional in-circuit emulation (ICE) or high-performance transaction-based acceleration. Combined with Veloce2, the latest-generation emulator from Mentor®, these PCI Express solutions deliver high-performance, and an easy-to-use system verification environment to develop new SoCs containing PCI Express Gen3 devices, without compromising delivery schedules.

Both solutions are available for deployment at customer sites effective immediately.

The Veloce2 emulator is a high-performance dual-mode accelerator/emulator, delivering twice the performance and capacity of previous generations for both transaction-based verification and traditional in-circuit emulation (ICE). With an extensive portfolio of vertical market solutions, the Veloce2 emulator is the platform of choice for networking, wireless, multimedia, storage, and embedded systems applications.

Pricing and Availability

For product information on the Mentor PCI Express Gen3 solutions, contact your Mentor Graphics sales representative, call 1-800-547-3000, or visit the website at www.mentor.com/med

(Mentor Graphics, Mentor, and Veloce are registered trademarks and iSolve is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

For more information contact

Carole Dunn
carole_dunn@mentor.com
Mentor Graphics
503-685-4716

Ry Schwark
ry_schwark@mentor.com
Mentor Graphics
503.685.1660

← Back to News

Siemens Digital Industries Software

Siemens Digital Industries Software

##TodayMeetsTomorrow

Solutions

  • Cloud
  • Mendix
  • Siemens EDA
  • MindSphere
  • Siemens PLM
  • View all portfolio

Explore

  • Digital Journeys
  • Community
  • Blog
  • Online Store

Siemens

  • About Us
  • Careers
  • Events
  • News and Press
  • Newsletter
  • Customer Stories

Contact Us

USA:

phone-office +1 800 547 3000

See our Worldwide Directory

  • Contact Us
  • Support Center
  • Give us Feedback
©2021 Siemens Digital Industries Software. All Rights Reserved.
Terms of Use Privacy Cookie Policy