The Best Verification Strategy You’ve Never Heard Of
Released on March 23rd, 2022
Authors: David Aerne, Amir Attarha, Harry Foster, Kurt Takara - Siemens EDA
The latest data from the bi-annual Wilson Research Group Functional Verification survey show that, despite more than a decade of effort in establishing new verification methodologies and techniques, the problem of how to produce functionally-correct ASIC or FPGA based electronic components is still a challenge. The median project schedule for both ASIC and FPGA projects is 10-12 months, which isn’t really that much time. Digging a little deeper, however, we see that over two thirds of the projects surveyed, both ASIC and FPGA, are completed behind schedule. A cynical observer might conclude that this also shows that one third of the respondents are lying, but even if that is not the case, clearly there is a problem.
View Video | Slides