Workshop
Estimating Power Dissipation of End-User Application on RTL
Released on March 23rd, 2022
Authors: Kevin Hotaling, Magdy El-Moursy - Siemens EDA
Overview:
A methodology to estimate the power dissipation of an end-user application on the Register Transfer Level (RTL) model of the target SoC platform is presented. Advanced Driving Assistance System (ADAS) of a vehicle is used as a case-study for the presented methodology. The methodology uses hybrid RTL simulation and emulation to run the heterogeneous automotive system. The methodology allows Software and Model to be included in the simulation Loop (known as Software and Model in the Loop, SiL and MiL, respectively).
Paper
Avoid the Pitfalls of Mixing Formal & Simulation Coverage
Released on March 23rd, 2022
Authors: Mark Eslinger, Joe Hupcey III, Nicolae Tusinschi - Siemens EDA
Overview:
Driven by the need to objectively measure the progress of their verification efforts, and the relative contributions of different verification techniques, customers have adopted “coverage” as a metric. However, what exactly is being measured is different depending on underlying verification technology in use. In this paper we will first review what these forms of “coverage” are telling the user, and how to merge them together in a manner that accurately reports status and expected behaviors.
Poster
Modeling Analog Devices using SV-RNM
Released on March 23rd, 2022
Author: Mariam Maurice - Siemens EDA
Overview:
This paper covers new technical thinking in modeling analog devices using defined nets, boundary elements and interconnects. How these definitions can help modeling analog devices such as DACs, ADCs, LDOs, Filters, and Image Sensor. Many debugging techniques are illustrated since debugging and visualization of RNM constructs are important during the integration of a complete analog device and during connecting an analog-modeled device to a digital one.