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  • Featured Papers, Posters & Tutorials from DVCon 2016

Featured Papers, Posters & Tutorials from DVCon 2016

The following papers, posters and tutorial interviews, were presented at DVCon 2016.

Featured Tutorials:

 

Advanced Validation & Verification Techniques for Complex Low Power SoCs

  • Overview
  • Tutorial Interview
  • Slides

Featuring: Joe Hupcey III, Gabriel Chidolue, Jonathan Lovett, Shantanu Samant

In this interview the presenters of the DVCon USA 2016 tutorial, “Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs” talk about the latest advances in low power design&verification introduced in the UPF 3.0 standard, and how it enables bit IP creators and IP customers to simplify their D&V flows.

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Back to Basics: Doing Formal “The Right Way”

  • Overview
  • Tutorial Interview
  • Slides

Featuring: Joe Hupcey III, Doug Smith, Mark Eslinger

In this interview the presenters of the DVCon USA 2016 tutorial, “Back to Basics: Doing Formal ‘The Right Way’” describe how D&V engineers can gradually adopt formal – enjoying correspondingly greater quality and schedule benefits starting automated formal apps through advanced property checking methodologies.

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DVCon US 2016: Featured Papers

Parameters, UVM, Coverage & Emulation – Take Two and Call Me in the Morning

Authors: Michael Horn, Bryan Ramirez and Hans van der Schoot - Mentor Graphics

Abstract:
Parameterized IP continues to expand in usage. Parameterized IP also continues to expand in size which compounds verification complexity. Previous DVCon papers have addressed issues related to using parameters with UVM [1] and employing code, functional and assertion coverage with parameterized IP [2]. They focused on these aspects for conventional simulation. However, with the growing use of emulation for hardware-assisted simulation acceleration, additional considerations emerge. What capabilities does the use of an emulator facilitate, or perhaps impede? How can this be exploited to verify parameterized IP faster and more efficiently?

No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model

Authors: Rich Edelman, Mentor Graphics

Abstract:
SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.

Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysis 

Authors: Avidan Efody, Mentor Graphics

Abstract:
Shrinking nodes and reduced supply voltages make transient faults due to electromagnetic interferences a growing concern for mission critical ASICs and FPGAs. To address this risk, the ISO 26262 safety automotive standard requires that the impacts of transient faults on safety goals are rigorously analyzed[1]. Such analysis is far from trivial, first and foremost due to the practically infinite number of fault and state combinations that could happen in a component's life cycle. This paper deals with transient fault analysis towards ISO 26262 certification. First we suggest a way to estimate ISO 26262 required metrics with a user specified level of accuracy using statistical sampling of transient faults. We then propose a technique that reuses existing regression results in order to minimize the resources required to analyze faults in both combinatorial and sequential elements.

Efficient Bug-Hunting Techniques Using Graph-Based Stimulus Models 

Authors: Nguyen Le, Microsoft Corp & Mike Andrews, Mentor Graphics

Abstract:
This paper describes how the emergence of graph-based stimulus modeling, as an alternative to constrained random generation, can be leveraged to apply certain bug hunting strategies in a simple and automated manner. These strategies, should, if the theoretical benefits are realized, provide verification engineers with a way to improve their bug detection rates while improving the efficiency of their regression runs by one or more orders of magnitude.

The paper combines a brief introduction to graph-based stimulus with some examples of promising bug hunting strategies, and then describe a series of experiments run on a real design to see if these strategies deliver the promised efficiency improvements in that case.

Verification Patterns – Taking Reuse to the Next Level

Authors: Harry Foster, Michael Horn, Bob Oden, Pradeep Salla and Hans van der Schoot - Mentor Graphics

Abstract:
Design patterns provide an optimized, reusable solution to many of today's engineering problems. Experience has shown that they are an effective tool for sharing best practices and building skills within a project team. However, one problem that has prevented the widespread adoption of design patterns within the microelectronic verification community is a lack of an easily searchable library of patterns. In this paper, we demonstrate a systematic set of guidelines for creating and organizing an extendable library of verification patterns that are applicable across multiple technologies and engines (or platforms) in the verification space—ranging from property specification to UVM testbench development—and formal verification, simulation, and emulation.

UPF Generic References: Unleashing The Full Potential 

Authors: Durgesh Prasad, Jitesh Bansal - Mentor Graphics

Abstract:
Power Aware verification is one of the tough challenges in the semiconductor industry. One of the key things to verify is the different power elements placed in the design. Unified Power Format (UPF) provides constructs such as bind_checker and query_command to ease this process [1]. The bind checker construct would require the access of UPF control signals as well as design element's component. For example, writing a custom assertion for a retention cell using bind checker might require reference to restore pin and retention clock pin. Although the retention elements pertaining to the same retention strategy would have the same restore pin but their clock might differ. This is where UPF generic references are helpful because they provide a single reserved UPF keyword to refer to different clock in the design and help users write a generic bind checker. Another usage of generic references is to specify custom retention strategy and custom isolation/level-shifter cells. In this paper we describe various Generic References provided by UPF and how they can be used to write very concise and scalable UPF.

Reset and Initialization, the Good, the Bad and the Ugly 

Authors: Kaowen Liu, MediaTek Inc & Ping Yeung, Mentor Graphics

Abstract:
One daunting challenge of developing a low-power SoC design is how to verify its power-up, reset and initialization sequences. All of the different parts of the design must reset correctly, before the start of functional operation. In particular, design registers must initialize properly before they are used. Our initialization verification methodology classifies design registers into three types: GOOD registers (those that are initialized properly), BAD registers (those that are not initialized) and UGLY registers (those that are initialized, but are subsequently corrupted). This paper presents our methodology for verifying these three types of design registers.

Activity Trend Guided Efficient Approach to Peak Power Estimation Using Emulation 

Authors: Gaurav Saharawat, Saurabh Jain and Madhur Bhatia - Mentor Graphics

Abstract:
With the advent of increasingly complex systems, the verification of SoC designs is becoming more challenging. Simulation and emulation are common technologies used to verify the functionality of a design-under-test (DUT) before tape-out, but with the expanding use of battery operated electronic devices; power has become a critical area for design verification. There are issues like excessive heating and supply voltage drops due to very high design activity at a particular point in time under special circumstances that can lead to incorrect hardware functionality or chip burnout. These types of power related issues are difficult to identify with traditional verification approaches creating the need to have a dedicated Power Verification and Estimation flow using the best technology available. Emulation is the most appropriate technology for uncovering real power bugs for long testbench run times and real SoC use modes. In a typical emulation based solution, the designer needs to dump waveform trace data for the complete duration of a testbench, and then the waveform data is fed as an input to power analysis tools to perform power computation of the SoC over the complete testbench time range and target functionality. This gives rise to the issue that it takes a very long time to generate such long waveforms, and the disk space requirements becomes gigantic for any meaningful test run. In addition, the power tool has to process a huge amount of waveform data, which adds more processing time before a designer can find out peak power consumption of the design. This practically renders the flow unusable over long, real testbenches, and designers tend to skip some tests and extrapolate the results obtained from smaller test runs. This leads to inaccuracies and can result in post-silicon respin issues. This situation is not unprecedented and requires an innovative solution, which this paper attempts to provide.

Slaying the UVM Reuse Dragon

  • Abstract
  • Poster
  • Paper

Slaying the UVM Reuse Dragon

Authors: Mike Baird, Willamette HDL & Bob Oden, Mentor Graphics

Abstract:
With larger and more complex designs the gap between design and verification has grown larger. Because of this the reuse of the testbench both in new projects and within the same project has become very desirable. One of the "promises" of UVM is achieving such reuse. However, in reality, UVM reuse has been limited. This paper identifies the issues that affect UVM reuse and strategies for achieving reuse. A UVM reuse methodology will be presented that provides reuse of components from one testbench to another and within the same testbench from block to chip level

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Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse

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  • Poster
  • Paper

Jump-Start Portable Stimulus Test Creation with SystemVerilog Reuse

Author: Matthew Ballance, Mentor Graphics

Abstract:
Design and verification have historically been driven by domain-specific languages. Reuse guidelines have long existed for reuse of a description within the same language or methodology, but do not exist for reusing a description across languages. An Accellera standardization effort around a Portable Stimulus Specification standard, and the existence in the industry of portable stimulus tools that can retarget an abstract test specification to multiple environments, provide a driver for the creation of such guidelines. This paper provides guidelines for structuring SystemVerilog stimulus and coverage specifications to maximize reuse with a portable stimulus specification language.

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Introspection Into SystemVerilog Without Turning It Inside Out

  • Abstract
  • Poster
  • Paper

Introspection Into SystemVerilog Without Turning It Inside Out

Author: Dave Rich, Mentor Graphics

Abstract:
Many times design engineers need to analyze their code beyond looking at simple functional behavior. How many bits of memory are in this design? How many places does the clock signal fan out to? And verification engineers need to dynamically modify their tests based on the result of the same kind of analysis. There are separate tools that provide some of this kind of analysis, and there is a programming language interface to write almost any application in C. but it would be much easier if SystemVerilog provided introspection – the ability to ask questions about your code from within your code. This paper presents a mechanism to add introspection using the existing DPI/VPI in an importable package along with an example of its use.

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A New Class Of Registers

  • Abstract
  • Poster
  • Paper

A New Class Of Registers

Authors: Mark Peryer & Dave Aerne, Mentor Graphics

Abstract:
The Universal Verification Methodology (UVM) register model provides a useful stimulus abstraction layer for register and memory access and for shadowing the content of hardware register content. However, the register model assumes the use of a simple parallel bus protocol, whereby a front door bus read or write is executed as a blocking transaction. This paper presents practical approaches to extending the reach of the register model abstraction layer to protocols which do not follow a simple completion model, based on the experience of developing a UVM library of Verification Intellectual Property (VIP).

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The Evolution of Triage - Real-time Improvements in Debug Productivity

  • Abstract
  • Poster
  • Paper

The Evolution of Triage - Real-time Improvements in Debug Productivity

Author: Gordon Allan, Mentor Graphics

Abstract:
The often overlooked topic of triage is explored in depth. Triage is that part of the design/verification process where failing test results from a regression run are prepared for analysis, categorized, dispatched to available resources where the real debug takes place. This activity can be a productivity drain, poorly executed, leading to iteration and waste. We describe triage techniques and an advanced flow which minimizes triage time, and maximizes productivity of subsequent debug.

Triage is the process of analysis of a discrete set of reported issues of common derivation, including a determination of priority and methodology for further exploration, analysis and ultimately resolution, of each issue, with the ultimate goal of making the most effective utilization of resources to achieve maximum benefit.

A recent job advertisement for a Triage Engineer role contained the following: “your success will be defined by the successful triage of incoming failed units, your triage throughput, the relationships you build,

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Verification with Multi-Core Parallel Simulations

  • Abstract
  • Poster
  • Paper

Verification with Multi-Core Parallel Simulations: Have You Found Your Sweet Spot Yet?

Authors: Rohit Jain & Shobana Sudhakar, Mentor Graphics

Abstract:
Despite the fact that parallel simulation technology is supported by almost all industry-leading simulator tools and the number of cores available in the machine servers is trending upward, the idea of multi-core simulations has not caught on in the user community. Successful multi-core parallel simulations depend on a variety of related design factors, which can be difficult to understand and sort out. Widespread analysis of different design scenarios have raised interesting observations about users’ perception and understanding of the technology, and also have helped make clear where it makes the most sense to use this technology and where it doesn’t. With suitable design applications, it is possible to significantly save verification cycles. On the other hand, frustrating results can arise if multi-core simulation technology is used in unsuitable scenarios. The key to success here, and the topic this paper explores, is knowing where to use the multi-core technology.

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Cross Coverage of Power States

  • Abstract
  • Poster
  • Paper

Cross Coverage of Power States

Authors: Veeresh Vikram Singh & Awashesh Kumar, Mentor Graphics

Abstract:
In today’s low power SoC design flow, the role of power states has grown up enormously. Power states represent operating modes of a low power design and its various elements. These elements can often be inter-connected or related to each other. This relationship is also reflected in their power state descriptions. So, it becomes important that verification engineers verify occurrences of possible combinations/crosses of power states. Power states of a low power design can be defined using add_power_state command of UPF - the IEEE standard to specify power intent. These are often composed in a hierarchical manner, i.e. power states of a higher level power domain are dependent over power states of lower level domains. There is no readymade coverage metric available to capture the inter-dependence of hierarchical power states. Covering only the states and transitions of a particular system would not ensure that its possible combinations with the power states of subsystems have also been covered. To capture such information, a cross coverage metric is most suited. This paper presents a coverage-metric that captures occurrences of such inter-dependence to ensure that the system works as expected in all possible combinations of power states. It discusses in detail the challenges faced in modeling such metric and defines a generic and customizable methodology to capture cross-coverage of power states. A cross of power states can be huge in size if not defined with appropriate consideration. Cross-coverage in such scenarios would become difficult to interpret. This paper also touches on some cases where a cross coverage metric will not be appropriate.

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Power State to PST Conversion

  • Abstract
  • Poster
  • Poster

Power State to PST Conversion: Simplifying Static Analysis and Debugging of Power Aware Designs

Authors: Madhur Bhargava, & Pankaj Gairola, Mentor Graphics

Abstract:
The increasing use of advanced power management techniques has led to great complexities in the low power verification process. Today’s chips have multiple power domains each having multiple operating power modes and dynamically changing voltage levels. Unified Power Format (UPF) provides specification of active power management for RTL designs to carry out the verification process. Accellera UPF provided commands to define the possible values of supply ports (“port states”) used to deliver power to a system, together with “power state tables” (or PSTs) that defined legal combinations of port states. Verification tools and engineers relied on PST-based analysis of the possible combinations of power supply values to determine where isolation and level shifting would be required in a given design. However, it effectively required implementation of power management in detail before verification could start, tending to delay power aware verification until later in the flow than necessary or require that verification be repeated later if earlier assumptions about implementation details proved to be incorrect. Also, Accellera UPF had no way of specifying power management requirements for IP components that might be used in a system. To address these issues, IEEE Std 1801 UPF added a number of new concepts such as supply-sets and power-states that enables users to construct complex power state definitions sufficient to model various possible situations. However, this additional flexibility often results in power state definitions that are difficult to understand, difficult to debug, and even more difficult for tools to analyze. In this paper, we highlight the power aware verification challenges involved for a design having power states defined using add_power_state command. Further, we demonstrate an approach to simplify the process of static analysis and debugging for such designs. This paper also includes guidelines to define power state definitions adhering to which can help ease the verification process.

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