Authors: Michael Horn, Bryan Ramirez and Hans van der Schoot - Mentor Graphics
Parameterized IP continues to expand in usage. Parameterized IP also continues to expand in size which compounds verification complexity. Previous DVCon papers have addressed issues related to using parameters with UVM  and employing code, functional and assertion coverage with parameterized IP . They focused on these aspects for conventional simulation. However, with the growing use of emulation for hardware-assisted simulation acceleration, additional considerations emerge. What capabilities does the use of an emulator facilitate, or perhaps impede? How can this be exploited to verify parameterized IP faster and more efficiently?
Authors: Rich Edelman, Mentor Graphics
SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.
Authors: Avidan Efody, Mentor Graphics
Shrinking nodes and reduced supply voltages make transient faults due to electromagnetic interferences a growing concern for mission critical ASICs and FPGAs. To address this risk, the ISO 26262 safety automotive standard requires that the impacts of transient faults on safety goals are rigorously analyzed. Such analysis is far from trivial, first and foremost due to the practically infinite number of fault and state combinations that could happen in a component's life cycle. This paper deals with transient fault analysis towards ISO 26262 certification. First we suggest a way to estimate ISO 26262 required metrics with a user specified level of accuracy using statistical sampling of transient faults. We then propose a technique that reuses existing regression results in order to minimize the resources required to analyze faults in both combinatorial and sequential elements.
Authors: Nguyen Le, Microsoft Corp & Mike Andrews, Mentor Graphics
This paper describes how the emergence of graph-based stimulus modeling, as an alternative to constrained random generation, can be leveraged to apply certain bug hunting strategies in a simple and automated manner. These strategies, should, if the theoretical benefits are realized, provide verification engineers with a way to improve their bug detection rates while improving the efficiency of their regression runs by one or more orders of magnitude.
The paper combines a brief introduction to graph-based stimulus with some examples of promising bug hunting strategies, and then describe a series of experiments run on a real design to see if these strategies deliver the promised efficiency improvements in that case.
Authors: Harry Foster, Michael Horn, Bob Oden, Pradeep Salla and Hans van der Schoot - Mentor Graphics
Design patterns provide an optimized, reusable solution to many of today's engineering problems. Experience has shown that they are an effective tool for sharing best practices and building skills within a project team. However, one problem that has prevented the widespread adoption of design patterns within the microelectronic verification community is a lack of an easily searchable library of patterns. In this paper, we demonstrate a systematic set of guidelines for creating and organizing an extendable library of verification patterns that are applicable across multiple technologies and engines (or platforms) in the verification space—ranging from property specification to UVM testbench development—and formal verification, simulation, and emulation.
Authors: Durgesh Prasad, Jitesh Bansal - Mentor Graphics
Power Aware verification is one of the tough challenges in the semiconductor industry. One of the key things to verify is the different power elements placed in the design. Unified Power Format (UPF) provides constructs such as bind_checker and query_command to ease this process . The bind checker construct would require the access of UPF control signals as well as design element's component. For example, writing a custom assertion for a retention cell using bind checker might require reference to restore pin and retention clock pin. Although the retention elements pertaining to the same retention strategy would have the same restore pin but their clock might differ. This is where UPF generic references are helpful because they provide a single reserved UPF keyword to refer to different clock in the design and help users write a generic bind checker. Another usage of generic references is to specify custom retention strategy and custom isolation/level-shifter cells. In this paper we describe various Generic References provided by UPF and how they can be used to write very concise and scalable UPF.
Authors: Kaowen Liu, MediaTek Inc & Ping Yeung, Mentor Graphics
One daunting challenge of developing a low-power SoC design is how to verify its power-up, reset and initialization sequences. All of the different parts of the design must reset correctly, before the start of functional operation. In particular, design registers must initialize properly before they are used. Our initialization verification methodology classifies design registers into three types: GOOD registers (those that are initialized properly), BAD registers (those that are not initialized) and UGLY registers (those that are initialized, but are subsequently corrupted). This paper presents our methodology for verifying these three types of design registers.
Authors: Gaurav Saharawat, Saurabh Jain and Madhur Bhatia - Mentor Graphics
With the advent of increasingly complex systems, the verification of SoC designs is becoming more challenging. Simulation and emulation are common technologies used to verify the functionality of a design-under-test (DUT) before tape-out, but with the expanding use of battery operated electronic devices; power has become a critical area for design verification. There are issues like excessive heating and supply voltage drops due to very high design activity at a particular point in time under special circumstances that can lead to incorrect hardware functionality or chip burnout. These types of power related issues are difficult to identify with traditional verification approaches creating the need to have a dedicated Power Verification and Estimation flow using the best technology available. Emulation is the most appropriate technology for uncovering real power bugs for long testbench run times and real SoC use modes. In a typical emulation based solution, the designer needs to dump waveform trace data for the complete duration of a testbench, and then the waveform data is fed as an input to power analysis tools to perform power computation of the SoC over the complete testbench time range and target functionality. This gives rise to the issue that it takes a very long time to generate such long waveforms, and the disk space requirements becomes gigantic for any meaningful test run. In addition, the power tool has to process a huge amount of waveform data, which adds more processing time before a designer can find out peak power consumption of the design. This practically renders the flow unusable over long, real testbenches, and designers tend to skip some tests and extrapolate the results obtained from smaller test runs. This leads to inaccuracies and can result in post-silicon respin issues. This situation is not unprecedented and requires an innovative solution, which this paper attempts to provide.