Featured Poster Paper from DVCon Europe 2015
Authors: Hans van der Schoot & Ahmed Yehia - Mentor Graphics
Abstract:
This paper demystifies the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. Architectural and modeling requirements are described, followed by a recommended systematic approach for maximizing overall testbench acceleration speed-up and achieving your ultimate performance expectations.
|
|
|