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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Advanced UVM
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      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
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      • Occurrence Property Patterns
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      • Start Here - Patterns Library Overview
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
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      • Configuring a Test Environment
      • Analysis Components & Techniques
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      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
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      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
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      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • Low Power Verification - 4/29
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Cadence, Mentor Graphics and Breker Announce Collaborative Technology Contribution to Accellera Portable Stimulus Working Group

Cadence, Mentor Graphics and Breker Announce Collaborative Technology Contribution to Accellera Portable Stimulus Working Group

SAN JOSE, Calif., Sept. 8, 2015 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), Mentor Graphics Corporation (NASDAQ: MENT) and Breker Verification Systems today announced that the three companies have collaborated on a technology contribution to the Accellera Portable Stimulus Working Group. The contribution leverages the combined experience of the three companies in providing portable test and stimulus solutions, and is intended to assist the Accellera Portable Stimulus Working Group in defining a system-on-chip (SoC) verification standard that offers both vertical (intellectual property to SoC) and horizontal (simulation to post-silicon) reuse of stimulus and test.

The collaborative contribution includes:

  • A concise specification language for use-cases that allows high level abstraction of stimulus and tests, including coverage and results checking
  • Semantics to allow generation of tests by automation tools in a variety of languages and tool environments with consistent behavior across multiple implementations from simulation through emulation to FPGA and post-silicon
  • A model-based approach supporting graph-based descriptions of stimulus and test scenarios
  • A library of predefined utility functions plus support for user-defined functions helpful when generating system-level portable stimulus and tests

For more information on the Portable Stimulus Working Group, visit http://www.accellera.org/activities/working-groups/portable-stimulus

"When we initiated the portable stimulus project within Accellera and offered technology we have in use today, we sought to collaborate with other leading vendors and their technologies to create a standard that would enjoy broad and rapid adoption," stated John Lenyo, vice president and general manager, Design Verification Technology Division at Mentor Graphics. "We are pleased to see this early collaborative effort to seed the Accellera Portable Stimulus Working Group result in a joint contribution that pulls these technologies together to help accelerate availability of a completed standard."

"Cadence believes portable stimulus will be the hallmark for the next generation of verification automation," said Ziv Binyamini, corporate vice president, research and development, Advanced Verification Solutions at Cadence. "Much like our collaboration on OVM and UVM standardization, this joint contribution offers a significant step toward creating a usable standard that can be supported by multiple vendors, and enables Cadence and our customers to leverage the current investments in our technology."

"Breker has been a vocal supporter of portable stimulus and our customers understand the need and value of our technology," said Adnan Hamid, CEO and co-founder of Breker Verification Systems. "The development of the standard and our joint contribution offer evidence of portable stimulus' progress from early adopter to mainstream technology."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

About Mentor

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.24 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.

About Breker

Electronic Design Automation (EDA) software company Breker Verification Systems provides innovative solutions to solve the challenge of complex system-on-chip (SoC) functional verification. Its products are used in production at leading semiconductor companies in the U.S., Europe and India. Founded in 2003, it is privately held and funded. More information about Breker can be found at www.brekersystems.com.

© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, and the Cadence logo, are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

For more information, please contact:

Cadence Newsroom
Cadence Design Systems, Inc.
408-944-7039
newsroom@cadence.com

Mentor Graphics
David Smith
503.685.1135
david_smith@mentor.com

Breker Verification Systems
Tom Anderson
408.823.9075
toma@brekersystems.com

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