Hans van der Schoot - Subject Matter Expert.
The new Acceleration of SystemVerilog Testbenches with Co-Emulation course is approximately 1 hour delivered in 4 sessions by Acceleration and Emulation Technologist, Dr. Hans van der Schoot. This course advocates that functional verification through modern testbenches paired with co-emulation enables further verification productivity improvements in terms of raw performance. Simulation paired with co-emulation will deliver dramatic speedup of execution of verification. This course on Acceleration of SystemVerilog Testbenches with Co-Emulation will give you the confidence required to start the process of investigating and creating a single testbench environment that can be used for both simulation as well as hardware-assisted acceleration.
This course is primarily aimed at existing SystemVerilog H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating SystemVerilog testbench environments.
This course may also be of interest to S/W engineers who demand earlier access to systems for S/W development.
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