WILSONVILLE, Ore., April 1, 2014 — Mentor Graphics Corp. (NASDAQ: MENT), today announced availability of a new solution for X-value verification in register transfer level (RTL) and gate level designs. X-values are symbols that represent unknown voltage levels of signals in digital IC designs. The latest version of the Questa® Verification Platform links simulation and formal verification capabilities to deliver complete X-value analysis and debug, which helps an IC design team avoid the risk of silicon and simulation failure. These new capabilities target both of the problematic effects of X-values that can lead to silicon bugs and wasted design effort: X-optimism and X-pessimism.
“Even though awareness of X issues is good, and designers do their best to follow coding guidelines to avoid X-state bugs, we still face the challenge of eliminating all X-related silicon bugs with traditional verification methods,” said Meng-Han Hsieh, director of Design Platform Division, MediaTek Inc. “The Questa X-value verification solution has proven to be of immense value in catching X bugs which would have been difficult to detect otherwise.”
“Within the Questa Platform we combine formal and simulation to obtain results that couldn’t be achieved with either of these technologies used independently,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “The X-value verification solution brings these complementary technologies together to help our customers overcome the risks of silicon and simulation failures caused by X-states.”
Simulation to Silicon Mismatches
Fundamental differences exist in the way that an X-value is interpreted in RTL simulation versus how it is treated by synthesis. The synthesis interpretation of X, as don’t care, can result in a silicon circuit that behaves differently than it does in RTL simulation, where X is interpreted as unknown. Simply eliminating all X-values from RTL simulation is not practical, as not all storage elements in today’s large designs can be reset directly, especially those in the data path.
X-Optimism and X-Pessimism Verification with Questa
X-optimism is the more dangerous of the two risks associated with X-values. This effect causes unknown values to act as though they were deterministically known values in RTL simulation. This can mask bugs, since the design is not being simulated with all the signal values that it will experience in silicon.
The Questa Verification Platform now includes a mode with silicon-accurate semantics for X-propagation in both the simulation and formal verification engines. This X-propagation mode defeats the threat of X-optimism by allowing X-values to propagate to assertions or testbench checkers, where they can be detected. The Questa fully automatic formal solution can detect storage elements that have been initialized correctly, but could later be corrupted by X-values in their fan-in logic. In addition, X-value debug is expedited with X-trapping that pinpoints the source of X-optimism in the design, and with X-tracing capabilities which aid in tracking down the source of unexpected X-values.
The second X-value concern is X-pessimism, which is most troublesome during gate-level simulation. This issue causes signal values to appear as unknown, even though they will be deterministically known in silicon. X-pessimism leads to wasted debug effort and overdesign.
The Questa solution eliminates these pessimistic X-values by identifying X-state signals that can be formally proven to always resolve to known good logic values. These logic values are then used to initialize the design in simulation, preventing costly simulation failures.
Product Availability and Additional Information
The new Questa product is available for immediate shipment. For more information, contact your Mentor Graphics sales associate or visit the company website at http://www.mentor.com/products/fv/questa-verification-platform.
About the Questa Verification Platform
The Questa Verification Platform uniquely provides a comprehensive solution that addresses the SoC verification explosion with a platform comprised of advanced verification methodologies, high performance simulation, intelligent testbench automation, software/hardware unified debug, formal, CDC, low power, analog-mixed signal, VIP, a central unified database and automated analysis tools, as well as integrated flows with ESL and emulation.
Mentor Graphics and Questa are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.